gpu: nvgpu: add gr ops for mpc exception handling

Required for t19x

JIRA GPUT19X-69

Change-Id: I96d1ee2ae1bf310ce572cb4dc7773818a42a25a0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515913
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 7 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index d853c4f0..c935809e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5634,8 +5634,9 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
                         + offset);
         u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
 
-        gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "");
-
+        gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
+                        "GPC%d TPC%d: pending exception 0x%x",
+                        gpc, tpc, tpc_exception);
 
         /* check if an sm exeption is pending */
         if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) ==
@@ -5682,6 +5683,10 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 ret = g->ops.gr.handle_tex_exception(g, gpc, tpc, post_event);
         }
 
+        if (g->ops.gr.handle_tpc_mpc_exception)
+                ret = g->ops.gr.handle_tpc_mpc_exception(g,
+                                        gpc, tpc, post_event);
+
         return ret;
 }