gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTX

This ioctl can be used on gp10b to set a flag in the context header
indicating this context should be run at elevated clock
frequency. FECS ctxsw ucode will read this flag as part of the context
switch and will request higher GPU clock frequencies from BPMP for the
duration of the context execution.

Bug 1819874

Change-Id: I84bf580923d95585095716d49cea24e58c9440ed
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1292746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0e1c88a4..170bfc7f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2109,6 +2109,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
         if (g->ops.gr.update_ctxsw_preemption_mode)
                 g->ops.gr.update_ctxsw_preemption_mode(g, ch_ctx, mem);
 
+        if (g->ops.gr.update_boosted_ctx)
+                g->ops.gr.update_boosted_ctx(g, mem, ch_ctx->gr_ctx);
+
         virt_addr_lo = u64_lo32(ch_ctx->patch_ctx.mem.gpu_va);
         virt_addr_hi = u64_hi32(ch_ctx->patch_ctx.mem.gpu_va);