gpu: nvgpu: gm20b: Regenerate clock gating lists

Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.

Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698

1 files changed, 13 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index cbad1292..661a2ca3 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4246,10 +4246,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
         if (g->ops.gr.init_gpc_mmu)
                 g->ops.gr.init_gpc_mmu(g);
 
-        /* slcg prod values */
-        g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
-        g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
-
         /* init mmu debug buffer */
         addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova);
         addr_lo = u64_lo32(addr);
@@ -4281,9 +4277,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gr_gk20a_zcull_init_hw(g, gr);
 
-        g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
-        g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
-
         if (g->elcg_enabled) {
                 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A);
                 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A);
@@ -4426,6 +4419,19 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
                         | mc_enable_blg_enabled_f()
                         | mc_enable_perfmon_enabled_f());
 
+        /* slcg prod values */
+        g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
+        if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod)
+                g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
+                                g->slcg_enabled);
+        g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
+
+        g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
+        if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
+                g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
+                                g->blcg_enabled);
+        g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
+
         /* enable fifo access */
         gk20a_writel(g, gr_gpfifo_ctl_r(),
                 gr_gpfifo_ctl_access_enabled_f() |