gpu: nvgpu: Removal of regops from CUDA driver

The current CUDA drivers have been using the regops to
directly accessing the GPU registers from user space through
the dbg node. This is a security hole and needs to be avoided.
The patch alternatively implements the similar functionality
in the kernel and provide an ioctl for it.

Bug 200083334

Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/711758
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 11 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 4217658c..7e8d4e13 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1273,7 +1273,6 @@ static int gr_gk20a_ctx_state_floorsweep(struct gk20a *g)
         u32 tpc_index, gpc_index;
         u32 tpc_offset, gpc_offset;
         u32 sm_id = 0, gpc_id = 0;
-        u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()];
         u32 tpc_per_gpc;
         u32 max_ways_evict = INVALID_MAX_WAYS;
         u32 l1c_dbg_reg_val;
@@ -1295,7 +1294,9 @@ static int gr_gk20a_ctx_state_floorsweep(struct gk20a *g)
                                 gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset,
                                              gr_gpc0_tpc0_pe_cfg_smid_value_f(sm_id));
 
-                                sm_id_to_gpc_id[sm_id] = gpc_index;
+                                g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index;
+                                g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index;
+
                                 sm_id++;
                         }
 
@@ -1306,6 +1307,8 @@ static int gr_gk20a_ctx_state_floorsweep(struct gk20a *g)
                 }
         }
 
+        gr->no_of_sm = sm_id;
+
         for (tpc_index = 0, gpc_id = 0;
              tpc_index < gr_pd_num_tpc_per_gpc__size_1_v();
              tpc_index++, gpc_id += 8) {
@@ -2997,6 +3000,7 @@ static void gk20a_remove_gr_support(struct gr_gk20a *gr)
         kfree(gr->pes_tpc_count[1]);
         kfree(gr->pes_tpc_mask[0]);
         kfree(gr->pes_tpc_mask[1]);
+        kfree(gr->sm_to_cluster);
         kfree(gr->gpc_skip_mask);
         kfree(gr->map_tiles);
         gr->gpc_tpc_count = NULL;
@@ -3089,6 +3093,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
         gr->pes_tpc_count[1] = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
         gr->pes_tpc_mask[0] = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
         gr->pes_tpc_mask[1] = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
+
         gr->gpc_skip_mask =
                 kzalloc(gr_pd_dist_skip_table__size_1_v() * 4 * sizeof(u32),
                         GFP_KERNEL);
@@ -3159,6 +3164,10 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
                 gr->gpc_skip_mask[gpc_index] = gpc_new_skip_mask;
         }
 
+        gr->sm_to_cluster = kzalloc(gr->gpc_count * gr->tpc_count *
+                                                        sizeof(struct sm_info), GFP_KERNEL);
+        gr->no_of_sm = 0;
+
         gk20a_dbg_info("fbps: %d", gr->num_fbps);
         gk20a_dbg_info("max_gpc_count: %d", gr->max_gpc_count);
         gk20a_dbg_info("max_fbps_count: %d", gr->max_fbps_count);