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authorTimo Alho <talho@nvidia.com>2018-03-05 02:31:06 -0500
committerTimo Alho <talho@nvidia.com>2018-03-05 11:39:57 -0500
commit848af2ce6de6140323a6ffe3075bf8021e119434 (patch)
treec89f28ac819f637b554f191da2f6a0fd8d75253e /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parent89fbf39a05483917c0a9f3453fd94c724bc37375 (diff)
Revert "Revert "Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"""
This reverts commit 89fbf39a05483917c0a9f3453fd94c724bc37375. Bug 2075315 Change-Id: Id34a0376be5160b164931926ec600f77edf69667 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1668487 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c33
1 files changed, 14 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index bdb54325..7160ab6f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -742,14 +742,13 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g,
742 742
743static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) 743static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block)
744{ 744{
745 u64 ptr = nvgpu_inst_block_addr(g, inst_block) >> 745 u32 ptr = u64_lo32(nvgpu_inst_block_addr(g, inst_block)
746 ram_in_base_shift_v(); 746 >> ram_in_base_shift_v());
747 u32 aperture = nvgpu_aperture_mask(g, inst_block, 747 u32 aperture = nvgpu_aperture_mask(g, inst_block,
748 gr_fecs_current_ctx_target_sys_mem_ncoh_f(), 748 gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
749 gr_fecs_current_ctx_target_sys_mem_coh_f(), 749 gr_fecs_current_ctx_target_vid_mem_f());
750 gr_fecs_current_ctx_target_vid_mem_f());
751 750
752 return gr_fecs_current_ctx_ptr_f(u64_lo32(ptr)) | aperture | 751 return gr_fecs_current_ctx_ptr_f(ptr) | aperture |
753 gr_fecs_current_ctx_valid_f(1); 752 gr_fecs_current_ctx_valid_f(1);
754} 753}
755 754
@@ -2172,18 +2171,16 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g)
2172 2171
2173 inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc); 2172 inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc);
2174 gk20a_writel(g, gr_fecs_new_ctx_r(), 2173 gk20a_writel(g, gr_fecs_new_ctx_r(),
2175 gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | 2174 gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) |
2176 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, 2175 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
2177 gr_fecs_new_ctx_target_sys_mem_ncoh_f(), 2176 gr_fecs_new_ctx_target_sys_mem_ncoh_f(),
2178 gr_fecs_new_ctx_target_sys_mem_coh_f(),
2179 gr_fecs_new_ctx_target_vid_mem_f()) | 2177 gr_fecs_new_ctx_target_vid_mem_f()) |
2180 gr_fecs_new_ctx_valid_m()); 2178 gr_fecs_new_ctx_valid_m());
2181 2179
2182 gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), 2180 gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(),
2183 gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | 2181 gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) |
2184 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, 2182 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
2185 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), 2183 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(),
2186 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(),
2187 gr_fecs_arb_ctx_ptr_target_vid_mem_f())); 2184 gr_fecs_arb_ctx_ptr_target_vid_mem_f()));
2188 2185
2189 gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); 2186 gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7);
@@ -4387,9 +4384,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4387 4384
4388 gk20a_writel(g, fb_mmu_debug_wr_r(), 4385 gk20a_writel(g, fb_mmu_debug_wr_r(),
4389 nvgpu_aperture_mask(g, &gr->mmu_wr_mem, 4386 nvgpu_aperture_mask(g, &gr->mmu_wr_mem,
4390 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), 4387 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4391 fb_mmu_debug_wr_aperture_sys_mem_coh_f(), 4388 fb_mmu_debug_wr_aperture_vid_mem_f()) |
4392 fb_mmu_debug_wr_aperture_vid_mem_f()) |
4393 fb_mmu_debug_wr_vol_false_f() | 4389 fb_mmu_debug_wr_vol_false_f() |
4394 fb_mmu_debug_wr_addr_f(addr)); 4390 fb_mmu_debug_wr_addr_f(addr));
4395 4391
@@ -4398,9 +4394,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4398 4394
4399 gk20a_writel(g, fb_mmu_debug_rd_r(), 4395 gk20a_writel(g, fb_mmu_debug_rd_r(),
4400 nvgpu_aperture_mask(g, &gr->mmu_rd_mem, 4396 nvgpu_aperture_mask(g, &gr->mmu_rd_mem,
4401 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), 4397 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4402 fb_mmu_debug_wr_aperture_sys_mem_coh_f(), 4398 fb_mmu_debug_rd_aperture_vid_mem_f()) |
4403 fb_mmu_debug_rd_aperture_vid_mem_f()) |
4404 fb_mmu_debug_rd_vol_false_f() | 4399 fb_mmu_debug_rd_vol_false_f() |
4405 fb_mmu_debug_rd_addr_f(addr)); 4400 fb_mmu_debug_rd_addr_f(addr));
4406 4401