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author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-28 02:53:48 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-28 12:47:03 -0500 |
commit | 830d3f10ca1f3d8a045542ef4548c84440a8e548 (patch) | |
tree | f968a340cb80a4d12074ef331b88e21beb1a15d8 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |
parent | ce06f74d6ba9eb495661c29eabcd6da2f52c7c8b (diff) |
gpu: nvgpu: cleanup uapi header includes
With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them
Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead
Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()
Jira NVGPU-363
Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 8a6db92c..64b54699 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -23,7 +23,6 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <trace/events/gk20a.h> | 25 | #include <trace/events/gk20a.h> |
26 | #include <uapi/linux/nvgpu.h> | ||
27 | 26 | ||
28 | #include <nvgpu/dma.h> | 27 | #include <nvgpu/dma.h> |
29 | #include <nvgpu/kmem.h> | 28 | #include <nvgpu/kmem.h> |
@@ -7892,7 +7891,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
7892 | "ctx op invalid offset: offset=0x%x", | 7891 | "ctx op invalid offset: offset=0x%x", |
7893 | ctx_ops[i].offset); | 7892 | ctx_ops[i].offset); |
7894 | ctx_ops[i].status = | 7893 | ctx_ops[i].status = |
7895 | NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_OFFSET; | 7894 | REGOP(STATUS_INVALID_OFFSET); |
7896 | continue; | 7895 | continue; |
7897 | } | 7896 | } |
7898 | if (!pm_ctx_ready) { | 7897 | if (!pm_ctx_ready) { |