diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-03-16 08:25:18 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-21 09:04:38 -0400 |
commit | 77b806fe7e68e853676f7c4bad14349aba1affa5 (patch) | |
tree | 2b0933a730d8b7f5144e0d51dfc89e3cb19a28f0 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |
parent | 66751bc05d7a1efca3668d59a2820e3e92985f91 (diff) |
gpu: nvgpu: gv100: fix PMA list alignment in ctxsw buffer
GV100 ucode is changed so that it expects LIST_nv_perf_pma_ctx_reg list in
ctxsw buffer to be 256 byte aligned but same change is not applied to other
chip ucodes
ADD new HAL (*add_ctxsw_reg_perf_pma) to configure PMA register list and
define a common HAL gr_gk20a_add_ctxsw_reg_perf_pma() for all other
chips except GV100
Define a separate HAL for GV100 gr_gv100_add_ctxsw_reg_perf_pma() and fix
the required alignment in this function
Bug 1998067
Change-Id: Ie172fe90e2cdbac2509f2ece953cd8552e66fc56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676655
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index bec33293..9d85a5ef 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -7568,6 +7568,15 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7568 | return 0; | 7568 | return 0; |
7569 | } | 7569 | } |
7570 | 7570 | ||
7571 | int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, | ||
7572 | struct aiv_list_gk20a *regs, | ||
7573 | u32 *count, u32 *offset, | ||
7574 | u32 max_cnt, u32 base, u32 mask) | ||
7575 | { | ||
7576 | return add_ctxsw_buffer_map_entries(map, regs, | ||
7577 | count, offset, max_cnt, base, mask); | ||
7578 | } | ||
7579 | |||
7571 | /* | 7580 | /* |
7572 | * PM CTXSW BUFFER LAYOUT : | 7581 | * PM CTXSW BUFFER LAYOUT : |
7573 | *|---------------------------------------------|0x00 <----PM CTXSW BUFFER BASE | 7582 | *|---------------------------------------------|0x00 <----PM CTXSW BUFFER BASE |
@@ -7671,7 +7680,7 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g) | |||
7671 | goto cleanup; | 7680 | goto cleanup; |
7672 | 7681 | ||
7673 | /* Add entries from _LIST_nv_perf_pma_ctx_reg*/ | 7682 | /* Add entries from _LIST_nv_perf_pma_ctx_reg*/ |
7674 | if (add_ctxsw_buffer_map_entries(map, &g->gr.ctx_vars.ctxsw_regs.perf_pma, | 7683 | if (g->ops.gr.add_ctxsw_reg_perf_pma(map, &g->gr.ctx_vars.ctxsw_regs.perf_pma, |
7675 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) | 7684 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) |
7676 | goto cleanup; | 7685 | goto cleanup; |
7677 | 7686 | ||