gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size

fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug

Bug 2093809

Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 51bb2551..d26d8a93 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -155,8 +155,10 @@ void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
                 gk20a_readl(g, gr_fecs_debug1_r()));
         nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x",
                 gk20a_readl(g, gr_fecs_debuginfo_r()));
+        nvgpu_err(g, "gr_fecs_ctxsw_status_1_r : 0x%x",
+                gk20a_readl(g, gr_fecs_ctxsw_status_1_r()));
 
-        for (i = 0; i < gr_fecs_ctxsw_mailbox__size_1_v(); i++)
+        for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++)
                 nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x",
                         i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i)));