gpu: nvgpu: Add CDE bits in FECS header

In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/802327
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 10 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0ae44c6f..24ee8876 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1612,7 +1612,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
         struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
         u32 virt_addr_lo;
         u32 virt_addr_hi;
-        u32 i, v, data;
+        u32 i, v, data, cde_v;
         int ret = 0;
         void *ctx_ptr = NULL;
 
@@ -1631,6 +1631,15 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
         if (!ctx_ptr)
                 return -ENOMEM;
 
+        /* Enable CDE in FECS header. Default cde = 0, is disabled,
+         * so no need to do anything in else {}
+         */
+        if (c->cde) {
+                cde_v = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0);
+                cde_v |=  ctxsw_prog_main_image_ctl_cde_enabled_f();
+                gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0, cde_v);
+        }
+
         for (i = 0; i < gr->ctx_vars.golden_image_size / 4; i++)
                 gk20a_mem_wr32(ctx_ptr, i, gr->ctx_vars.local_golden_image[i]);