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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-05-14 08:22:49 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:10:05 -0400
commit6b33379c55a8368ce9e5ed1381f9aeeebe383dfe (patch)
tree625ae2366c0b21d9c4b18255f691f506debfcbfb /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parentcd13ee4aafcdb0206078e9e41aca53107235bbed (diff)
gpu: nvgpu: Rewrite PMU boot-up sequence
Rewrite PMU boot sequence as a state machine. At PMU power-up send initial messages, and reset state machine. At each reply from PMU, do the next stage of PMU boot and set state. As now PMU and FECS boot are independent, we need to ensure engine idle before saving ZBC. Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410205
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c21
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3d70afd5..b23bb540 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3534,7 +3534,7 @@ clean_up:
3534 return ret; 3534 return ret;
3535} 3535}
3536 3536
3537static void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) 3537void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
3538{ 3538{
3539 struct fifo_gk20a *f = &g->fifo; 3539 struct fifo_gk20a *f = &g->fifo;
3540 struct fifo_engine_info_gk20a *gr_info = 3540 struct fifo_engine_info_gk20a *gr_info =
@@ -4569,9 +4569,19 @@ int gk20a_init_gr_support(struct gk20a *g)
4569 if (err) 4569 if (err)
4570 return err; 4570 return err;
4571 4571
4572 /* GR is inialized, signal possible waiters */
4573 g->gr.initialized = true;
4574 wake_up(&g->gr.init_wq);
4575
4572 return 0; 4576 return 0;
4573} 4577}
4574 4578
4579/* Wait until GR is initialized */
4580void gk20a_gr_wait_initialized(struct gk20a *g)
4581{
4582 wait_event(g->gr.init_wq, g->gr.initialized);
4583}
4584
4575#define NVA297_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc 4585#define NVA297_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
4576#define NVA297_SET_CIRCULAR_BUFFER_SIZE 0x1280 4586#define NVA297_SET_CIRCULAR_BUFFER_SIZE 0x1280
4577#define NVA297_SET_SHADER_EXCEPTIONS 0x1528 4587#define NVA297_SET_SHADER_EXCEPTIONS 0x1528
@@ -5550,6 +5560,8 @@ int gk20a_gr_suspend(struct gk20a *g)
5550 5560
5551 gk20a_gr_flush_channel_tlb(&g->gr); 5561 gk20a_gr_flush_channel_tlb(&g->gr);
5552 5562
5563 g->gr.initialized = false;
5564
5553 gk20a_dbg_fn("done"); 5565 gk20a_dbg_fn("done");
5554 return ret; 5566 return ret;
5555} 5567}
@@ -6816,7 +6828,12 @@ void gr_gk20a_commit_global_pagepool(struct gk20a *g,
6816 gr_pd_pagepool_valid_true_f(), patch); 6828 gr_pd_pagepool_valid_true_f(), patch);
6817} 6829}
6818 6830
6819void gk20a_init_gr(struct gpu_ops *gops) 6831void gk20a_init_gr(struct gk20a *g)
6832{
6833 init_waitqueue_head(&g->gr.init_wq);
6834}
6835
6836void gk20a_init_gr_ops(struct gpu_ops *gops)
6820{ 6837{
6821 gops->gr.access_smpc_reg = gr_gk20a_access_smpc_reg; 6838 gops->gr.access_smpc_reg = gr_gk20a_access_smpc_reg;
6822 gops->gr.bundle_cb_defaults = gr_gk20a_bundle_cb_defaults; 6839 gops->gr.bundle_cb_defaults = gr_gk20a_bundle_cb_defaults;