gpu: nvgpu: do not include hw_proj_*.h

hw_proj_gk20a.h and hw_proj_gm20b.h should not be
included, hence remove the includes and APIs used
from the header

Use nvgpu_get_litter_value() API to replace use
of header

Bug 200156699

Change-Id: I5e88f71657682dd94ac7f0a45f940b70cf8222e7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1129611
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 12 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3354c05e..2c7423c0 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -58,7 +58,6 @@
 #include "semaphore_gk20a.h"
 #include "platform_gk20a.h"
 #include "ctxsw_trace_gk20a.h"
-#include "hw_proj_gk20a.h"
 
 #define BLK_SIZE (256)
 #define NV_PMM_FBP_STRIDE       0x1000
@@ -5513,8 +5512,10 @@ static int gk20a_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
 {
         int sm_id;
         struct gr_gk20a *gr = &g->gr;
-        u32 offset = proj_gpc_stride_v() * gpc +
-                     proj_tpc_in_gpc_stride_v() * tpc;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
+                                               GPU_LIT_TPC_IN_GPC_STRIDE);
+        u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 
         mutex_lock(&g->dbg_sessions_lock);
 
@@ -5542,6 +5543,9 @@ static int gk20a_gr_update_sm_error_state(struct gk20a *g,
         u32 gpc, tpc, offset;
         struct gr_gk20a *gr = &g->gr;
         struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
+                                               GPU_LIT_TPC_IN_GPC_STRIDE);
         int err = 0;
 
         mutex_lock(&g->dbg_sessions_lock);
@@ -5564,8 +5568,7 @@ static int gk20a_gr_update_sm_error_state(struct gk20a *g,
         gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
         tpc = g->gr.sm_to_cluster[sm_id].tpc_index;
 
-        offset = proj_gpc_stride_v() * gpc +
-                     proj_tpc_in_gpc_stride_v() * tpc;
+        offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 
         if (gk20a_is_channel_ctx_resident(ch)) {
                 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
@@ -5607,6 +5610,9 @@ static int gk20a_gr_clear_sm_error_state(struct gk20a *g,
         u32 gpc, tpc, offset;
         u32 val;
         struct gr_gk20a *gr = &g->gr;
+        u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+        u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
+                                               GPU_LIT_TPC_IN_GPC_STRIDE);
         int err = 0;
 
         mutex_lock(&g->dbg_sessions_lock);
@@ -5623,8 +5629,7 @@ static int gk20a_gr_clear_sm_error_state(struct gk20a *g,
                 gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
                 tpc = g->gr.sm_to_cluster[sm_id].tpc_index;
 
-                offset = proj_gpc_stride_v() * gpc +
-                             proj_tpc_in_gpc_stride_v() * tpc;
+                offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
 
                 val = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
                 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,