gpu: nvgpu: improve sched err handling

bug 200114561

1) when handling sched error, if CTXSW status reads switch
check FECS mailbox register to know whether next or current
channel caused error
2) Update recovery function to use ch id passed to it
3) Recovery function now passes mmu_engine_id to mmu fault
handler instead of fifo_engine_id

Change-Id: I3576cc4a90408b2f76b2c42cce19c27344531b1c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/763538
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index cf9cab0e..501a7deb 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5581,7 +5581,7 @@ int gk20a_gr_isr(struct gk20a *g)
 
         if (need_reset)
                 gk20a_fifo_recover(g, BIT(ENGINE_GR_GK20A),
-                                   ~(u32)0, false, true);
+                                   ~(u32)0, false, false, true);
 
 clean_up:
         if (gr_intr && !ch) {