diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 13:55:40 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:42 -0400 |
commit | 4728761b6cd002404b9ccd8b318cc9f772962efb (patch) | |
tree | 5062ec39c067b33445e91f43e7ada45a65d5c6f6 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |
parent | 9891cb117e538f1ea5d19171a3c88422cdce7162 (diff) |
gpu: nvgpu: add get_sm_no_lock_down_hww_global_esr_mask gr ops
This is required to take care of t19x changes to support
multiple SM
JIRA GPUT19X-75
Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index b714b2e2..d325f794 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5527,16 +5527,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
5527 | bool disable_sm_exceptions = true; | 5527 | bool disable_sm_exceptions = true; |
5528 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | 5528 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); |
5529 | bool sm_debugger_attached; | 5529 | bool sm_debugger_attached; |
5530 | u32 global_esr, warp_esr; | 5530 | u32 global_esr, warp_esr, global_mask; |
5531 | |||
5532 | /* these three interrupts don't require locking down the SM. They can | ||
5533 | * be handled by usermode clients as they aren't fatal. Additionally, | ||
5534 | * usermode clients may wish to allow some warps to execute while others | ||
5535 | * are at breakpoints, as opposed to fatal errors where all warps should | ||
5536 | * halt. */ | ||
5537 | u32 global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | ||
5538 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
5539 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
5540 | 5531 | ||
5541 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); | 5532 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); |
5542 | 5533 | ||
@@ -5545,6 +5536,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
5545 | global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); | 5536 | global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); |
5546 | *hww_global_esr = global_esr; | 5537 | *hww_global_esr = global_esr; |
5547 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); | 5538 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); |
5539 | global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g); | ||
5548 | 5540 | ||
5549 | if (!sm_debugger_attached) { | 5541 | if (!sm_debugger_attached) { |
5550 | nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x", | 5542 | nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x", |
@@ -8387,9 +8379,7 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state) | |||
8387 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp | 8379 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp |
8388 | * masks. | 8380 | * masks. |
8389 | */ | 8381 | */ |
8390 | global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | 8382 | global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g); |
8391 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
8392 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
8393 | 8383 | ||
8394 | /* Lock down all SMs */ | 8384 | /* Lock down all SMs */ |
8395 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { | 8385 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { |
@@ -8499,3 +8489,19 @@ u32 gk20a_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) | |||
8499 | return hww_global_esr; | 8489 | return hww_global_esr; |
8500 | } | 8490 | } |
8501 | 8491 | ||
8492 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) | ||
8493 | { | ||
8494 | /* | ||
8495 | * These three interrupts don't require locking down the SM. They can | ||
8496 | * be handled by usermode clients as they aren't fatal. Additionally, | ||
8497 | * usermode clients may wish to allow some warps to execute while others | ||
8498 | * are at breakpoints, as opposed to fatal errors where all warps should | ||
8499 | * halt. | ||
8500 | */ | ||
8501 | u32 global_esr_mask = | ||
8502 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | ||
8503 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
8504 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
8505 | |||
8506 | return global_esr_mask; | ||
8507 | } | ||