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authorDeepak Nibade <dnibade@nvidia.com>2018-04-06 08:56:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-10 14:23:03 -0400
commit4314771142e0b68810b8fa86ec45b6f6b4e24651 (patch)
tree32c1916385ecdb63073400e07e85266df5f8d412 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parente1200259ba3ad4ae416990b2f2abccb94565430f (diff)
gpu: nvgpu: add broadcast address decode support for volta
With Volta we have more number of broadcast registers than previous chips and we don't decode them right now in gr_gk20a_decode_priv_addr() Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all previous chips Add and use gr_gv11b_decode_priv_addr() for Volta gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set the broadcast flags apporiately Define below new broadcast types PRI_BROADCAST_FLAGS_PMMGPC PRI_BROADCAST_FLAGS_PMM_GPCS PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB PRI_BROADCAST_FLAGS_PMMFBP PRI_BROADCAST_FLAGS_PMM_FBPS PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP Bug 200398811 Jira NVGPU-556 Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690026 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 65144cc5..3912a1df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6247,7 +6247,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
6247 u32 *priv_offset); 6247 u32 *priv_offset);
6248 6248
6249/* This function will decode a priv address and return the partition type and numbers. */ 6249/* This function will decode a priv address and return the partition type and numbers. */
6250static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, 6250int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
6251 int *addr_type, /* enum ctxsw_addr_type */ 6251 int *addr_type, /* enum ctxsw_addr_type */
6252 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, 6252 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
6253 u32 *broadcast_flags) 6253 u32 *broadcast_flags)
@@ -6365,7 +6365,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g,
6365 6365
6366 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); 6366 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
6367 6367
6368 err = gr_gk20a_decode_priv_addr(g, addr, &addr_type, 6368 err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
6369 &gpc_num, &tpc_num, &ppc_num, &be_num, 6369 &gpc_num, &tpc_num, &ppc_num, &be_num,
6370 &broadcast_flags); 6370 &broadcast_flags);
6371 gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type); 6371 gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
@@ -7211,7 +7211,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
7211 7211
7212 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); 7212 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
7213 7213
7214 err = gr_gk20a_decode_priv_addr(g, addr, &addr_type, 7214 err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
7215 &gpc_num, &tpc_num, &ppc_num, &be_num, 7215 &gpc_num, &tpc_num, &ppc_num, &be_num,
7216 &broadcast_flags); 7216 &broadcast_flags);
7217 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, 7217 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,