gpu: nvgpu: calculate zcull_sm_num_rcp using tpc_count

old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage

bug 1553171

Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/500517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index dde57494..93649675 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4006,8 +4006,9 @@ static int gr_gk20a_zcull_init_hw(struct gk20a *g, struct gr_gk20a *gr)
                         floorsweep = true;
         }
 
-        /* 1.0f / 1.0f * gr_gpc0_zcull_sm_num_rcp_conservative__max_v() */
-        rcp_conserv = gr_gpc0_zcull_sm_num_rcp_conservative__max_v();
+        /* ceil(1.0f / SM_NUM * gr_gpc0_zcull_sm_num_rcp_conservative__max_v()) */
+        rcp_conserv = DIV_ROUND_UP(gr_gpc0_zcull_sm_num_rcp_conservative__max_v(),
+                gr->gpc_tpc_count[0]);
 
         for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
                 offset = gpc_index * proj_gpc_stride_v();