gpu: nvgpu: Use coherent aperture flag

When using a coherent DMA API wee must make sure to program
any aperture fields with the coherent aperture setting. To
do this the nvgpu_aperture_mask() function was modified to
take a third aperture mask argument, a coherent setting, so
that code can use this function to generate coherent aperture
settings.

The aperture choice is some what tricky: the default version
of this function uses the state of the DMA API to determine
what aperture to use for SYSMEM: either coherent or
non-coherent internally. Thus a kernel user need only specify
the normal nvgpu_mem struct and the correct mask should be
chosen. Due to many uses of nvgpu_mem structs not created
directly from the DMA API wrapper it's easier to translate
SYSMEM to SYSMEM_COH after creation.

However, the GMMU mapping code, will encounter buffers from
userspace with difference coerency attributes than the DMA
API. Thus the __nvgpu_aperture_mask() really respects the
aperture setting passed in regardless of the DMA API state.
This aperture setting is pulled from NVGPU_VM_MAP_IO_COHERENT
since this is either passed in from userspace or set by the
kernel when using coherent DMA. The aperture field in attrs
is upgraded to coh if this flag is set.

This change also adds a coherent sysmem mask everywhere that
it can. There's a couple places that do not have a coherent
register field defined yet. These need to eventually be
defined and added.

Lastly the aperture mask code has been mvoed from the Linux
vm.c code to the general vm.c code since this function has
no Linux dependencies.

Note: depends on https://git-master.nvidia.com/r/1664536 for
new register fields.

JIRA EVLR-2333

Change-Id: I4b347911ecb7c511738563fe6c34d0e6aa380d71
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655220
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6ae743ef..2cde10ec 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -745,8 +745,9 @@ static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block)
         u64 ptr = nvgpu_inst_block_addr(g, inst_block) >>
                 ram_in_base_shift_v();
         u32 aperture = nvgpu_aperture_mask(g, inst_block,
-                        gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
-                        gr_fecs_current_ctx_target_vid_mem_f());
+                                gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
+                                gr_fecs_current_ctx_target_sys_mem_coh_f(),
+                                gr_fecs_current_ctx_target_vid_mem_f());
 
         return gr_fecs_current_ctx_ptr_f(u64_lo32(ptr)) | aperture |
                 gr_fecs_current_ctx_valid_f(1);
@@ -2171,16 +2172,18 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g)
 
         inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc);
         gk20a_writel(g, gr_fecs_new_ctx_r(),
-                        gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) |
-                        nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
+                     gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) |
+                     nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
                                 gr_fecs_new_ctx_target_sys_mem_ncoh_f(),
+                                gr_fecs_new_ctx_target_sys_mem_coh_f(),
                                 gr_fecs_new_ctx_target_vid_mem_f()) |
-                        gr_fecs_new_ctx_valid_m());
+                     gr_fecs_new_ctx_valid_m());
 
         gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(),
-                        gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) |
-                        nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
+                     gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) |
+                     nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
                                 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(),
+                                gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(),
                                 gr_fecs_arb_ctx_ptr_target_vid_mem_f()));
 
         gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7);
@@ -4379,8 +4382,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gk20a_writel(g, fb_mmu_debug_wr_r(),
                      nvgpu_aperture_mask(g, &gr->mmu_wr_mem,
-                       fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
-                       fb_mmu_debug_wr_aperture_vid_mem_f()) |
+                                fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
+                                fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
+                                fb_mmu_debug_wr_aperture_vid_mem_f()) |
                      fb_mmu_debug_wr_vol_false_f() |
                      fb_mmu_debug_wr_addr_f(addr));
 
@@ -4389,8 +4393,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gk20a_writel(g, fb_mmu_debug_rd_r(),
                      nvgpu_aperture_mask(g, &gr->mmu_rd_mem,
-                       fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
-                       fb_mmu_debug_rd_aperture_vid_mem_f()) |
+                                fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
+                                fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
+                                fb_mmu_debug_rd_aperture_vid_mem_f()) |
                      fb_mmu_debug_rd_vol_false_f() |
                      fb_mmu_debug_rd_addr_f(addr));