diff options
author | David Nieto <dmartineznie@nvidia.com> | 2017-10-23 16:58:37 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-26 20:56:08 -0400 |
commit | 0f8746130ba79ec82a4b0675bbe00ab1ba17d3f8 (patch) | |
tree | 697a3965e29d4e55f053e3a8fd7bb94aac8aa844 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |
parent | 00e52529a8431a6520b8e1bbcbfa44b4cc86be80 (diff) |
gpu: nvgpu: halify size of patch buffer
Allow per chip calculation of gr patch buffer size
and set default to match hw default of 512 data-address pair entries (4K)
bug 200350539
Change-Id: I6010c9e0304332825cb02612d3f10523ef27d128
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584033
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 71fe44a3..3c3ddc80 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -714,7 +714,8 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, | |||
714 | if (patch) { | 714 | if (patch) { |
715 | u32 patch_slot = ch_ctx->patch_ctx.data_count * | 715 | u32 patch_slot = ch_ctx->patch_ctx.data_count * |
716 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; | 716 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; |
717 | if (patch_slot > (PATCH_CTX_SLOTS_MAX - | 717 | if (patch_slot > (PATCH_CTX_ENTRIES_FROM_SIZE( |
718 | ch_ctx->patch_ctx.mem.size) - | ||
718 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY)) { | 719 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY)) { |
719 | nvgpu_err(g, "failed to access patch_slot %d", | 720 | nvgpu_err(g, "failed to access patch_slot %d", |
720 | patch_slot); | 721 | patch_slot); |
@@ -2813,17 +2814,29 @@ static void gr_gk20a_free_channel_gr_ctx(struct channel_gk20a *c) | |||
2813 | c->ch_ctx.gr_ctx = NULL; | 2814 | c->ch_ctx.gr_ctx = NULL; |
2814 | } | 2815 | } |
2815 | 2816 | ||
2817 | u32 gr_gk20a_get_patch_slots(struct gk20a *g) | ||
2818 | { | ||
2819 | return PATCH_CTX_SLOTS_PER_PAGE; | ||
2820 | } | ||
2821 | |||
2816 | static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g, | 2822 | static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g, |
2817 | struct channel_gk20a *c) | 2823 | struct channel_gk20a *c) |
2818 | { | 2824 | { |
2819 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; | 2825 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; |
2820 | struct vm_gk20a *ch_vm = c->vm; | 2826 | struct vm_gk20a *ch_vm = c->vm; |
2827 | u32 alloc_size; | ||
2821 | int err = 0; | 2828 | int err = 0; |
2822 | 2829 | ||
2823 | gk20a_dbg_fn(""); | 2830 | gk20a_dbg_fn(""); |
2824 | 2831 | ||
2832 | alloc_size = g->ops.gr.get_patch_slots(g) * | ||
2833 | PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY; | ||
2834 | |||
2835 | nvgpu_log(g, gpu_dbg_info, "patch buffer size in entries: %d", | ||
2836 | alloc_size); | ||
2837 | |||
2825 | err = nvgpu_dma_alloc_map_flags_sys(ch_vm, NVGPU_DMA_NO_KERNEL_MAPPING, | 2838 | err = nvgpu_dma_alloc_map_flags_sys(ch_vm, NVGPU_DMA_NO_KERNEL_MAPPING, |
2826 | PATCH_CTX_SLOTS_MAX * sizeof(u32), &patch_ctx->mem); | 2839 | alloc_size * sizeof(u32), &patch_ctx->mem); |
2827 | if (err) | 2840 | if (err) |
2828 | return err; | 2841 | return err; |
2829 | 2842 | ||