gpu: nvgpu: support context regoptype for egpc/etpc

- add is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops
- add gr ops for decode and create egpc/etpc priv addr
- add etpc as part of ctxsw_regs

JIRA GPUT19X-49
Bug  200311674
Bug  1960226

Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Change-Id: I9a8be1804a9354238de2441093b3b136321b7e53
Reviewed-on: https://git-master.nvidia.com/r/1522442
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
index 58e62d32..1676fb9a 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -76,6 +76,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
                             &g->gr.ctx_vars.ctxsw_regs.ppc.count);
         gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0,
                             &g->gr.ctx_vars.ctxsw_regs.etpc.count);
+        gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
+                            &g->gr.ctx_vars.ctxsw_regs.ppc.count);
 
         err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst);
         err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data);