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authorArto Merilainen <amerilainen@nvidia.com>2014-03-19 03:38:25 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:08:53 -0400
commita9785995d5f22aaeb659285f8aeb64d8b56982e0 (patch)
treecc75f75bcf43db316a002a7a240b81f299bf6d7f /drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
parent61efaf843c22b85424036ec98015121c08f5f16c (diff)
gpu: nvgpu: Add NVIDIA GPU Driver
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c256
1 files changed, 256 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
new file mode 100644
index 00000000..12bba1fd
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -0,0 +1,256 @@
1/*
2 * drivers/video/tegra/host/gk20a/gr_ctx_sim_gk20a.c
3 *
4 * GK20A Graphics Context for Simulation
5 *
6 * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "gk20a.h"
23#include "gr_ctx_gk20a.h"
24
25int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
26{
27 int err = 0;
28 u32 i, temp;
29 char *size_path = NULL;
30 char *reg_path = NULL;
31 char *value_path = NULL;
32
33 gk20a_dbg(gpu_dbg_fn | gpu_dbg_info,
34 "querying grctx info from chiplib");
35
36 g->gr.ctx_vars.dynamic = true;
37 g->gr.netlist = GR_NETLIST_DYNAMIC;
38
39 /* query sizes and counts */
40 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0,
41 &g->gr.ctx_vars.ucode.fecs.inst.count);
42 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0,
43 &g->gr.ctx_vars.ucode.fecs.data.count);
44 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0,
45 &g->gr.ctx_vars.ucode.gpccs.inst.count);
46 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0,
47 &g->gr.ctx_vars.ucode.gpccs.data.count);
48 gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp);
49 g->gr.ctx_vars.buffer_size = temp << 2;
50 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0,
51 &g->gr.ctx_vars.sw_bundle_init.count);
52 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0,
53 &g->gr.ctx_vars.sw_method_init.count);
54 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
55 &g->gr.ctx_vars.sw_ctx_load.count);
56
57 switch (0) { /*g->gr.ctx_vars.reg_init_override)*/
58#if 0
59 case NV_REG_STR_RM_GR_REG_INIT_OVERRIDE_PROD_DIFF:
60 sizePath = "GRCTX_NONCTXSW_PROD_DIFF_REG_SIZE";
61 regPath = "GRCTX_NONCTXSW_PROD_DIFF_REG:REG";
62 valuePath = "GRCTX_NONCTXSW_PROD_DIFF_REG:VALUE";
63 break;
64#endif
65 default:
66 size_path = "GRCTX_NONCTXSW_REG_SIZE";
67 reg_path = "GRCTX_NONCTXSW_REG:REG";
68 value_path = "GRCTX_NONCTXSW_REG:VALUE";
69 break;
70 }
71
72 gk20a_sim_esc_readl(g, size_path, 0,
73 &g->gr.ctx_vars.sw_non_ctx_load.count);
74
75 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0,
76 &g->gr.ctx_vars.ctxsw_regs.sys.count);
77 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0,
78 &g->gr.ctx_vars.ctxsw_regs.gpc.count);
79 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0,
80 &g->gr.ctx_vars.ctxsw_regs.tpc.count);
81#if 0
82 /* looks to be unused, actually chokes the sim */
83 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
84 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
85#endif
86 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0,
87 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count);
88 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0,
89 &g->gr.ctx_vars.ctxsw_regs.pm_sys.count);
90 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0,
91 &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count);
92 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0,
93 &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count);
94
95 err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.fecs.inst);
96 err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.fecs.data);
97 err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.gpccs.inst);
98 err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.gpccs.data);
99 err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_bundle_init);
100 err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_method_init);
101 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.sw_ctx_load);
102 err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_non_ctx_load);
103 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.sys);
104 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.gpc);
105 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.tpc);
106 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.zcull_gpc);
107 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.ppc);
108 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_sys);
109 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_gpc);
110 err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_tpc);
111
112 if (err)
113 goto fail;
114
115 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++)
116 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS",
117 i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]);
118
119 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++)
120 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS",
121 i, &g->gr.ctx_vars.ucode.fecs.data.l[i]);
122
123 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++)
124 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS",
125 i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]);
126
127 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++)
128 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS",
129 i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]);
130
131 for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) {
132 struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l;
133 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR",
134 i, &l[i].addr);
135 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE",
136 i, &l[i].value);
137 }
138
139 for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) {
140 struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l;
141 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR",
142 i, &l[i].addr);
143 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE",
144 i, &l[i].value);
145 }
146
147 for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) {
148 struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l;
149 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR",
150 i, &l[i].addr);
151 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX",
152 i, &l[i].index);
153 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE",
154 i, &l[i].value);
155 }
156
157 for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) {
158 struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l;
159 gk20a_sim_esc_readl(g, reg_path, i, &l[i].addr);
160 gk20a_sim_esc_readl(g, value_path, i, &l[i].value);
161 }
162
163 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
164 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
165 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
166 i, &l[i].addr);
167 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX",
168 i, &l[i].index);
169 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE",
170 i, &l[i].value);
171 }
172
173 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) {
174 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l;
175 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR",
176 i, &l[i].addr);
177 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX",
178 i, &l[i].index);
179 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE",
180 i, &l[i].value);
181 }
182
183 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) {
184 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l;
185 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR",
186 i, &l[i].addr);
187 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX",
188 i, &l[i].index);
189 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE",
190 i, &l[i].value);
191 }
192
193 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) {
194 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l;
195 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR",
196 i, &l[i].addr);
197 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX",
198 i, &l[i].index);
199 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE",
200 i, &l[i].value);
201 }
202
203 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) {
204 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l;
205 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR",
206 i, &l[i].addr);
207 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX",
208 i, &l[i].index);
209 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE",
210 i, &l[i].value);
211 }
212
213 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) {
214 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l;
215 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR",
216 i, &l[i].addr);
217 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX",
218 i, &l[i].index);
219 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE",
220 i, &l[i].value);
221 }
222
223 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) {
224 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l;
225 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR",
226 i, &l[i].addr);
227 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX",
228 i, &l[i].index);
229 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE",
230 i, &l[i].value);
231 }
232
233 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) {
234 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l;
235 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR",
236 i, &l[i].addr);
237 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX",
238 i, &l[i].index);
239 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE",
240 i, &l[i].value);
241 }
242
243 g->gr.ctx_vars.valid = true;
244
245 gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0,
246 &g->gr.ctx_vars.regs_base_index);
247
248 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib");
249 return 0;
250fail:
251 gk20a_err(dev_from_gk20a(g),
252 "failed querying grctx info from chiplib");
253 return err;
254
255}
256
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