gpu: nvgpu: initialze bundle64 state

We receive bundle with address and 64 bit values from ucode on some platforms
This patch adds the support to handle 64 bit values

Add struct av64_gk20a to store an address and corresponding 64 bit value
Add struct av64_list_gk20a to store count and list of av64_gk20a

Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit
values

In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT,
load the bundle64 state into above local structures

Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle()
if defined

Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim()

Jira NVGPUT-96

Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1736450
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
index 01c7ed3c..6d6352df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -63,6 +63,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
                             &g->gr.ctx_vars.sw_ctx_load.count);
         g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
                             &g->gr.ctx_vars.sw_veid_bundle_init.count);
+        g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT_SIZE", 0,
+                            &g->gr.ctx_vars.sw_bundle64_init.count);
 
         g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
                             &g->gr.ctx_vars.sw_non_ctx_load.count);
@@ -92,6 +94,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
         err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.inst);
         err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.data);
         err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_bundle_init);
+        err |= !alloc_av64_list_gk20a(g, &g->gr.ctx_vars.sw_bundle64_init);
         err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_method_init);
         err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.sw_ctx_load);
         err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_non_ctx_load);
@@ -168,6 +171,17 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
                                     i, &l[i].value);
         }
 
+        for (i = 0; i < g->gr.ctx_vars.sw_bundle64_init.count; i++) {
+                struct av64_gk20a *l = g->gr.ctx_vars.sw_bundle64_init.l;
+
+                g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:ADDR",
+                                i, &l[i].addr);
+                g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_LO",
+                                i, &l[i].value_lo);
+                g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_HI",
+                                i, &l[i].value_hi);
+        }
+
         for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
                 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
                 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",