diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-07-27 20:06:36 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-10-11 12:16:03 -0400 |
commit | fda4ddfa79f3a78becfe44fd558974bd274c03a9 (patch) | |
tree | 55d7999d7af7040ed50121fa6fa70fddc11b0887 /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | bb5fd16c67287e53db5165a974ea15ec3be09fe9 (diff) |
gpu: nvgpu: userd allocation from sysmem
When bar1 memory is not supported then userd will be
allocated from sysmem.
Functions gp_get and gp_put are updated accordingly.
JIRA GV11B-1
Change-Id: Ia895712a110f6cca26474228141488f5f8ace756
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1225384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2b55dd26..042bd9d7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -342,6 +342,7 @@ struct gpu_ops { | |||
342 | void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); | 342 | void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); |
343 | } clock_gating; | 343 | } clock_gating; |
344 | struct { | 344 | struct { |
345 | int (*init_fifo_setup_hw)(struct gk20a *g); | ||
345 | void (*bind_channel)(struct channel_gk20a *ch_gk20a); | 346 | void (*bind_channel)(struct channel_gk20a *ch_gk20a); |
346 | void (*unbind_channel)(struct channel_gk20a *ch_gk20a); | 347 | void (*unbind_channel)(struct channel_gk20a *ch_gk20a); |
347 | void (*disable_channel)(struct channel_gk20a *ch); | 348 | void (*disable_channel)(struct channel_gk20a *ch); |
@@ -386,6 +387,8 @@ struct gpu_ops { | |||
386 | u32 *runlist); | 387 | u32 *runlist); |
387 | void (*get_ch_runlist_entry)(struct channel_gk20a *ch, | 388 | void (*get_ch_runlist_entry)(struct channel_gk20a *ch, |
388 | u32 *runlist); | 389 | u32 *runlist); |
390 | u32 (*userd_gp_get)(struct gk20a *g, struct channel_gk20a *ch); | ||
391 | void (*userd_gp_put)(struct gk20a *g, struct channel_gk20a *ch); | ||
389 | } fifo; | 392 | } fifo; |
390 | struct pmu_v { | 393 | struct pmu_v { |
391 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 394 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
@@ -552,6 +555,7 @@ struct gpu_ops { | |||
552 | u32 (*get_big_page_sizes)(void); | 555 | u32 (*get_big_page_sizes)(void); |
553 | u32 (*get_physical_addr_bits)(struct gk20a *g); | 556 | u32 (*get_physical_addr_bits)(struct gk20a *g); |
554 | int (*init_mm_setup_hw)(struct gk20a *g); | 557 | int (*init_mm_setup_hw)(struct gk20a *g); |
558 | bool (*is_bar1_supported)(struct gk20a *g); | ||
555 | int (*init_bar2_vm)(struct gk20a *g); | 559 | int (*init_bar2_vm)(struct gk20a *g); |
556 | int (*init_bar2_mm_hw_setup)(struct gk20a *g); | 560 | int (*init_bar2_mm_hw_setup)(struct gk20a *g); |
557 | void (*remove_bar2_vm)(struct gk20a *g); | 561 | void (*remove_bar2_vm)(struct gk20a *g); |