gpu: nvgpu: add HALs to submit and wait for runlist

Add below two new HALs
gops.fifo.runlist_hw_submit() to submit a new runlist to hardware
gops.fifo.runlist_wait_pending() to wait until runlist write is successful

Set existing API gk20a_fifo_runlist_wait_pending() to
gops.fifo.runlist_wait_pending HAL

Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w
and set it to gops.fifo.runlist_hw_submit HAL

Jira NVGPUT-20

Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700548
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 57854e11..ba27f5d9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -669,6 +669,9 @@ struct gpu_ops {
                                 u64 *base_gpuva, u32 *sync_size);
                 u32 (*get_syncpt_incr_per_release)(void);
 #endif
+                void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id,
+                        u32 count, u32 buffer_index);
+                int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
         } fifo;
         struct pmu_v {
                 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);