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authorDeepak Nibade <dnibade@nvidia.com>2018-01-16 06:07:37 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-07 18:35:47 -0500
commitf0cbe19b12524f5df6466eaf86acbfb349def6b1 (patch)
treebed8a312e29592d41d9de4afb331756c2d38fb96 /drivers/gpu/nvgpu/gk20a/gk20a.h
parent0c8deb74aff6d0781cdf3278f56d7bce42b16a67 (diff)
gpu: nvgpu: add user API to get read-only syncpoint address map
Add User space API NVGPU_AS_IOCTL_GET_SYNC_RO_MAP to get read-only syncpoint address map in user space We already map whole syncpoint shim to each address space with base address being vm->syncpt_ro_map_gpu_va This new API exposes this base GPU_VA address of syncpoint map, and unit size of each syncpoint to user space. User space can then calculate address of each syncpoint as syncpoint_address = base_gpu_va + (syncpoint_id * syncpoint_unit_size) Note that this syncpoint address is read_only, and should be only used for inserting semaphore acquires. Adding semaphore release with this address would result in MMU_FAULT Define new HAL g->ops.fifo.get_sync_ro_map and set this for all GPUs supported on Xavier SoC Bug 200327559 Change-Id: Ica0db48fc28fdd0ff2a5eb09574dac843dc5e4fd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1649365 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5e46344a..02c7d0d9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -617,6 +617,8 @@ struct gpu_ops {
617 bool wfi_cmd, struct priv_cmd_entry *cmd, 617 bool wfi_cmd, struct priv_cmd_entry *cmd,
618 u32 id, u64 gpu_va); 618 u32 id, u64 gpu_va);
619 u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); 619 u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd);
620 int (*get_sync_ro_map)(struct vm_gk20a *vm,
621 u64 *base_gpuva, u32 *sync_size);
620#endif 622#endif
621 } fifo; 623 } fifo;
622 struct pmu_v { 624 struct pmu_v {