gpu: nvgpu: SM/TEX exception handling support

Add TEX exception handling support. Also make SM exception handler into
a function pointer, which should allow different chips to implement
their own SM exception handling routine.

Bug 1635727
Bug 1637486

Change-Id: I429905726c1840c11e83780843d82729495dc6a5
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935329

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 0207588f..24c062d2 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -202,6 +202,10 @@ struct gpu_ops {
                                 struct channel_gk20a *fault_ch,
                                 bool *early_exit, bool *ignore_debugger);
                 u32 (*mask_hww_warp_esr)(u32 hww_warp_esr);
+                int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc,
+                        bool *post_event, struct channel_gk20a *fault_ch);
+                int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
+                                                bool *post_event);
         } gr;
         const char *name;
         struct {