gpu: nvgpu: Move programming of host registers to fifo

Move code that touches host registers and instance block to fifo HAL.
This involves adding HAL ops for the fifo HAL functions that get
called from outside fifo. This clears responsibility of channel by
leaving it only managing channels in software and push buffers.

channel had member ramfc defined, but it was not used, to remove it.

pbdma_acquire_val consisted both of channel logic and hardware
programming. The channel logic was moved to the caller and only
hardware programming was moved.

Change-Id: Id005787f6cc91276b767e8e86325caf966913de9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1322423
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c8932d63..4f50ae36 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -398,7 +398,9 @@ struct gpu_ops {
                 int (*alloc_inst)(struct gk20a *g, struct channel_gk20a *ch);
                 void (*free_inst)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*setup_ramfc)(struct channel_gk20a *c, u64 gpfifo_base,
-                                u32 gpfifo_entries, u32 flags);
+                                u32 gpfifo_entries,
+                                unsigned long acquire_timeout,
+                                u32 flags);
                 int (*resetup_ramfc)(struct channel_gk20a *c);
                 int (*preempt_channel)(struct gk20a *g, u32 hw_chid);
                 int (*preempt_tsg)(struct gk20a *g, u32 tsgid);
@@ -456,6 +458,8 @@ struct gpu_ops {
                         unsigned int id_type, unsigned int timeout_rc_type);
                 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
                 int (*reset_enable_hw)(struct gk20a *g);
+                int (*setup_userd)(struct channel_gk20a *c);
+                u32 (*pbdma_acquire_val)(u64 timeout);
         } fifo;
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/