gpu: nvgpu: fix pmu->mscg_stat optimization issue

- with help of WRITE_ONCE() & ACCESS_ONCE()
  make sure variable pmu->mscg_stat read/write goes through
  without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
  to support backward compatibility

issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat

JIRA DNVGPU-71

Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5e2344cf..692f054f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -64,6 +64,10 @@ struct acr_desc;
 #endif
 #include "gm206/bios_gm206.h"
 
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
+#define WRITE_ONCE(x, val) \
+                        x = val
+#endif
 
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
     32 ns is the resolution of ptimer. */