gpu: nvgpu: Idle GR before calling PMU ZBC save

On gk20a when PMU is updating ZBC colors it is reading them from L2.
But L2 has one port, and ZBC reads can race with other transactions.
Idle graphics before sending PMU the ZBC_UPDATE request.

Also makes pmu_save_zbc a HAL, because PMU ucode has changes to bypass
this problem on some chips.

Bug 1746047

Change-Id: Id8fcd6850af7ef1d8f0a6aafa0fe6b4f88b5f2d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1129017

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5c397ad8..47adcc14 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -188,6 +188,9 @@ struct gpu_ops {
                                 struct zbc_entry *zbc_val);
                 int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr,
                                 struct zbc_query_params *query_params);
+                void (*pmu_save_zbc)(struct gk20a *g, u32 entries);
+                int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr,
+                                struct zbc_entry *zbc_val);
                 u32 (*pagepool_default_size)(struct gk20a *g);
                 int (*init_ctx_state)(struct gk20a *g);
                 int (*alloc_gr_ctx)(struct gk20a *g,