gpu: nvgpu: use chip specific zbc_c/z format reg

Use chip specific gpcs_swdx_dss_zbc_c_format_reg
and gpcs_swdx_dss_zbc_z_format_reg. These registers
are different for gv11b/gv100 from gp10b/gp106.

Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d9a8396f..a1c9c2bd 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * GK20A Graphics
  *
@@ -437,6 +437,8 @@ struct gpu_ops {
                 unsigned long (*get_max_gfxp_wfi_timeout_count)
                                         (struct gk20a *g);
                 void (*ecc_init_scrub_reg)(struct gk20a *g);
+                u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g);
+                u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);