gpu: nvgpu: add and reorg reset_enable_hw fifo ops

fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts
after all the required configuration such as configuring timeouts,
enabling timeout detections are taken care of.

JIRA GPUT19X-74
JIRA GPUT19X-47

Change-Id: Id780cc11d858db18f8d748c037954ede73298506
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325351
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 4e1c4ff4..ce26125d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -456,6 +456,7 @@ struct gpu_ops {
                 int (*preempt_ch_tsg)(struct gk20a *g, u32 id,
                         unsigned int id_type, unsigned int timeout_rc_type);
                 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
+                int (*reset_enable_hw)(struct gk20a *g);
         } fifo;
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/