gpu: nvgpu: add init_pbdma_intr_desc fifo ops

Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks for each GPU version separately

pbdma_intr_0 field differences for each GPU version:-
-gk20a  : bit 28 does not exists in hw
-gm20b  : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw
-gp10b  : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28,
          (syncpoint_illegal) added in hw but is not being handled.
-gk20a/gm20b/gp10b
bit 24 eng_reset and bit 25 semaphore always existed in hw but never
handled

JIRA GPUT19X-47

Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8d03cc9a..817315e7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -454,6 +454,7 @@ struct gpu_ops {
                         unsigned int id_type, unsigned int timeout_rc_type);
                 int (*preempt_ch_tsg)(struct gk20a *g, u32 id,
                         unsigned int id_type, unsigned int timeout_rc_type);
+                void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
         } fifo;
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/