gpu: nvgpu: Split out pramin code

Split out the pramin interface code in preparation for splitting
out the mem_desc code.

JIRA NVGPU-12

Change-Id: I3f03447ea213cc15669b0934fa706e7cb22599b7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1323323
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 88acc3ec..451e32ca 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -40,6 +40,7 @@ struct dbg_profiler_object_data;
 
 #include "../../../arch/arm/mach-tegra/iomap.h"
 
+#include <nvgpu/pramin.h>
 #include <nvgpu/acr/nvgpu_acr.h>
 
 #include "as_gk20a.h"
@@ -70,6 +71,8 @@ struct dbg_profiler_object_data;
                         x = val
 #endif
 
+struct page_alloc_chunk;
+
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
     32 ns is the resolution of ptimer. */
 #define PTIMER_REF_FREQ_HZ                      31250000
@@ -648,6 +651,13 @@ struct gpu_ops {
                 bool (*mmu_fault_pending)(struct gk20a *g);
         } mm;
         struct {
+                u32 (*enter)(struct gk20a *g, struct mem_desc *mem,
+                             struct page_alloc_chunk *chunk, u32 w);
+                void (*exit)(struct gk20a *g, struct mem_desc *mem,
+                             struct page_alloc_chunk *chunk);
+                u32 (*data032_r)(u32 i);
+        } pramin;
+        struct {
                 int (*init_therm_setup_hw)(struct gk20a *g);
                 int (*elcg_init_idle_filters)(struct gk20a *g);
                 void (*therm_debugfs_init)(struct gk20a *g);