diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-03-21 15:55:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-06 21:14:53 -0400 |
commit | c9665079d7b12f22a847c62587724b4ee120ca6e (patch) | |
tree | 7882bd08193db4c34b3b8ad7df7013339da2fba1 /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | b69020bff5dfa69cad926c9374cdbe9a62509ffd (diff) |
gpu: nvgpu: rename mem_desc to nvgpu_mem
Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index db7b3c5d..4fa8b76f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -258,7 +258,7 @@ struct gpu_ops { | |||
258 | struct gr_ctx_desc *gr_ctx); | 258 | struct gr_ctx_desc *gr_ctx); |
259 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, | 259 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, |
260 | struct channel_ctx_gk20a *ch_ctx, | 260 | struct channel_ctx_gk20a *ch_ctx, |
261 | struct mem_desc *mem); | 261 | struct nvgpu_mem *mem); |
262 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, | 262 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, |
263 | struct channel_gk20a *c, | 263 | struct channel_gk20a *c, |
264 | bool enable); | 264 | bool enable); |
@@ -279,7 +279,7 @@ struct gpu_ops { | |||
279 | u32 expect_delay); | 279 | u32 expect_delay); |
280 | void (*init_cyclestats)(struct gk20a *g); | 280 | void (*init_cyclestats)(struct gk20a *g); |
281 | void (*enable_cde_in_fecs)(struct gk20a *g, | 281 | void (*enable_cde_in_fecs)(struct gk20a *g, |
282 | struct mem_desc *mem); | 282 | struct nvgpu_mem *mem); |
283 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, | 283 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, |
284 | u64 sms, bool enable); | 284 | u64 sms, bool enable); |
285 | void (*bpt_reg_info)(struct gk20a *g, | 285 | void (*bpt_reg_info)(struct gk20a *g, |
@@ -329,7 +329,7 @@ struct gpu_ops { | |||
329 | u32 compute_preempt_mode); | 329 | u32 compute_preempt_mode); |
330 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); | 330 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); |
331 | void (*update_boosted_ctx)(struct gk20a *g, | 331 | void (*update_boosted_ctx)(struct gk20a *g, |
332 | struct mem_desc *mem, | 332 | struct nvgpu_mem *mem, |
333 | struct gr_ctx_desc *gr_ctx); | 333 | struct gr_ctx_desc *gr_ctx); |
334 | int (*fuse_override)(struct gk20a *g); | 334 | int (*fuse_override)(struct gk20a *g); |
335 | void (*init_sm_id_table)(struct gk20a *g); | 335 | void (*init_sm_id_table)(struct gk20a *g); |
@@ -344,11 +344,11 @@ struct gpu_ops { | |||
344 | int (*commit_global_timeslice)(struct gk20a *g, | 344 | int (*commit_global_timeslice)(struct gk20a *g, |
345 | struct channel_gk20a *c, bool patch); | 345 | struct channel_gk20a *c, bool patch); |
346 | int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); | 346 | int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); |
347 | void (*restore_context_header)(struct gk20a *g, struct mem_desc *ctxheader); | 347 | void (*restore_context_header)(struct gk20a *g, struct nvgpu_mem *ctxheader); |
348 | void (*write_zcull_ptr)(struct gk20a *g, | 348 | void (*write_zcull_ptr)(struct gk20a *g, |
349 | struct mem_desc *mem, u64 gpu_va); | 349 | struct nvgpu_mem *mem, u64 gpu_va); |
350 | void (*write_pm_ptr)(struct gk20a *g, | 350 | void (*write_pm_ptr)(struct gk20a *g, |
351 | struct mem_desc *mem, u64 gpu_va); | 351 | struct nvgpu_mem *mem, u64 gpu_va); |
352 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); | 352 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); |
353 | void (*load_tpc_mask)(struct gk20a *g); | 353 | void (*load_tpc_mask)(struct gk20a *g); |
354 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); | 354 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); |
@@ -372,7 +372,7 @@ struct gpu_ops { | |||
372 | int (*vpr_info_fetch)(struct gk20a *g); | 372 | int (*vpr_info_fetch)(struct gk20a *g); |
373 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 373 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
374 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 374 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
375 | void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); | 375 | void (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); |
376 | void (*hub_isr)(struct gk20a *g); | 376 | void (*hub_isr)(struct gk20a *g); |
377 | } fb; | 377 | } fb; |
378 | struct { | 378 | struct { |
@@ -636,7 +636,7 @@ struct gpu_ops { | |||
636 | void (*l2_flush)(struct gk20a *g, bool invalidate); | 636 | void (*l2_flush)(struct gk20a *g, bool invalidate); |
637 | void (*cbc_clean)(struct gk20a *g); | 637 | void (*cbc_clean)(struct gk20a *g); |
638 | void (*set_big_page_size)(struct gk20a *g, | 638 | void (*set_big_page_size)(struct gk20a *g, |
639 | struct mem_desc *mem, int size); | 639 | struct nvgpu_mem *mem, int size); |
640 | u32 (*get_big_page_sizes)(void); | 640 | u32 (*get_big_page_sizes)(void); |
641 | u32 (*get_physical_addr_bits)(struct gk20a *g); | 641 | u32 (*get_physical_addr_bits)(struct gk20a *g); |
642 | int (*init_mm_setup_hw)(struct gk20a *g); | 642 | int (*init_mm_setup_hw)(struct gk20a *g); |
@@ -646,19 +646,19 @@ struct gpu_ops { | |||
646 | void (*remove_bar2_vm)(struct gk20a *g); | 646 | void (*remove_bar2_vm)(struct gk20a *g); |
647 | const struct gk20a_mmu_level * | 647 | const struct gk20a_mmu_level * |
648 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); | 648 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); |
649 | void (*init_pdb)(struct gk20a *g, struct mem_desc *inst_block, | 649 | void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block, |
650 | struct vm_gk20a *vm); | 650 | struct vm_gk20a *vm); |
651 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, | 651 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, |
652 | u32 flags); | 652 | u32 flags); |
653 | size_t (*get_vidmem_size)(struct gk20a *g); | 653 | size_t (*get_vidmem_size)(struct gk20a *g); |
654 | void (*init_inst_block)(struct mem_desc *inst_block, | 654 | void (*init_inst_block)(struct nvgpu_mem *inst_block, |
655 | struct vm_gk20a *vm, u32 big_page_size); | 655 | struct vm_gk20a *vm, u32 big_page_size); |
656 | bool (*mmu_fault_pending)(struct gk20a *g); | 656 | bool (*mmu_fault_pending)(struct gk20a *g); |
657 | } mm; | 657 | } mm; |
658 | struct { | 658 | struct { |
659 | u32 (*enter)(struct gk20a *g, struct mem_desc *mem, | 659 | u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, |
660 | struct page_alloc_chunk *chunk, u32 w); | 660 | struct page_alloc_chunk *chunk, u32 w); |
661 | void (*exit)(struct gk20a *g, struct mem_desc *mem, | 661 | void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, |
662 | struct page_alloc_chunk *chunk); | 662 | struct page_alloc_chunk *chunk); |
663 | u32 (*data032_r)(u32 i); | 663 | u32 (*data032_r)(u32 i); |
664 | } pramin; | 664 | } pramin; |
@@ -709,7 +709,7 @@ struct gpu_ops { | |||
709 | bool (*is_priv_load)(u32 falcon_id); | 709 | bool (*is_priv_load)(u32 falcon_id); |
710 | void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); | 710 | void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); |
711 | int (*alloc_blob_space)(struct gk20a *g, | 711 | int (*alloc_blob_space)(struct gk20a *g, |
712 | size_t size, struct mem_desc *mem); | 712 | size_t size, struct nvgpu_mem *mem); |
713 | int (*pmu_populate_loader_cfg)(struct gk20a *g, | 713 | int (*pmu_populate_loader_cfg)(struct gk20a *g, |
714 | void *lsfm, u32 *p_bl_gen_desc_size); | 714 | void *lsfm, u32 *p_bl_gen_desc_size); |
715 | int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, | 715 | int (*flcn_populate_bl_dmem_desc)(struct gk20a *g, |
@@ -820,7 +820,7 @@ struct gpu_ops { | |||
820 | void (*init_hw)(struct gk20a *g); | 820 | void (*init_hw)(struct gk20a *g); |
821 | void (*isr)(struct gk20a *g); | 821 | void (*isr)(struct gk20a *g); |
822 | int (*read_ptimer)(struct gk20a *g, u64 *value); | 822 | int (*read_ptimer)(struct gk20a *g, u64 *value); |
823 | int (*bar1_bind)(struct gk20a *g, struct mem_desc *bar1_inst); | 823 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
824 | } bus; | 824 | } bus; |
825 | 825 | ||
826 | int (*bios_init)(struct gk20a *g); | 826 | int (*bios_init)(struct gk20a *g); |