gpu: nvgpu: add sched control API

Added a dedicated device node to allow an
app manager to control TSG scheduling parameters:
- Get list of TSGs
- Get list of recent TSGs
- Get list of TSGs per pid
- Get TSG current scheduling parameters
- Set TSG timeslice
- Set TSG runlist interleave

Jira VFND-1586

Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1160384
(cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e)
Reviewed-on: http://git-master/r/1167021
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c5da68cc..8aa8689b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -52,6 +52,7 @@ struct acr_desc;
 #include "acr.h"
 #include "cde_gk20a.h"
 #include "debug_gk20a.h"
+#include "sched_gk20a.h"
 
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
     32 ns is the resolution of ptimer. */
@@ -817,6 +818,11 @@ struct gk20a {
                 struct device *node;
         } ctxsw;
 
+        struct {
+                struct cdev cdev;
+                struct device *node;
+        } sched;
+
         struct mutex client_lock;
         int client_refcount; /* open channels and ctrl nodes */
 
@@ -847,6 +853,8 @@ struct gk20a {
         struct gk20a_ctxsw_trace *ctxsw_trace;
         struct gk20a_fecs_trace *fecs_trace;
 
+        struct gk20a_sched_ctrl sched_ctrl;
+
         struct device_dma_parameters dma_parms;
 
         struct gk20a_cde_app cde_app;
@@ -925,6 +933,7 @@ enum gk20a_dbg_categories {
         gpu_dbg_cde     = BIT(10), /* cde info messages */
         gpu_dbg_cde_ctx = BIT(11), /* cde context usage messages */
         gpu_dbg_ctxsw   = BIT(12), /* ctxsw tracing */
+        gpu_dbg_sched   = BIT(13), /* sched control tracing */
         gpu_dbg_mem     = BIT(31), /* memory accesses, very verbose */
 };