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authorseshendra Gadagottu <sgadagottu@nvidia.com>2017-03-17 14:30:57 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-05-26 17:07:12 -0400
commitc0822cb22e13204e06b145ae950a33d45e95918e (patch)
tree1623fcd5db0d24190e6d93287742c8d2fee14794 /drivers/gpu/nvgpu/gk20a/gk20a.h
parente21e6e947b334cd16cc92c41953bf3c0153b1508 (diff)
gpu: nvgpu: add chip specific sync point support
Added support for chip specific sync point implementation. Relevant fifo hal functions are added and updated for legacy chips. JIRA GPUT19X-2 Change-Id: I9a9c36d71e15c384b5e5af460cd52012f94e0b04 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1258232 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 29ac4763..f246b857 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -499,6 +499,20 @@ struct gpu_ops {
499 unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, 499 unsigned int (*handle_pbdma_intr_0)(struct gk20a *g,
500 u32 pbdma_id, u32 pbdma_intr_0, 500 u32 pbdma_id, u32 pbdma_intr_0,
501 u32 *handled, u32 *error_notifier); 501 u32 *handled, u32 *error_notifier);
502#ifdef CONFIG_TEGRA_GK20A_NVHOST
503 int (*alloc_syncpt_buf)(struct channel_gk20a *c,
504 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
505 void (*free_syncpt_buf)(struct channel_gk20a *c,
506 struct nvgpu_mem *syncpt_buf);
507 void (*add_syncpt_wait_cmd)(struct gk20a *g,
508 struct priv_cmd_entry *cmd, u32 off,
509 u32 id, u32 thresh, u64 gpu_va);
510 u32 (*get_syncpt_wait_cmd_size)(void);
511 void (*add_syncpt_incr_cmd)(struct gk20a *g,
512 bool wfi_cmd, struct priv_cmd_entry *cmd,
513 u32 id, u64 gpu_va);
514 u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd);
515#endif
502 } fifo; 516 } fifo;
503 struct pmu_v { 517 struct pmu_v {
504 /*used for change of enum zbc update cmd id from ver 0 to ver1*/ 518 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
@@ -1243,6 +1257,13 @@ struct gk20a {
1243 /* Some boards might be missing power sensor, preventing 1257 /* Some boards might be missing power sensor, preventing
1244 * from monitoring power, current and voltage */ 1258 * from monitoring power, current and voltage */
1245 bool power_sensor_missing; 1259 bool power_sensor_missing;
1260
1261#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
1262 phys_addr_t syncpt_unit_base;
1263 size_t syncpt_unit_size;
1264 u32 syncpt_size;
1265#endif
1266
1246}; 1267};
1247 1268
1248static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) 1269static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)