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authorSeema Khowala <seemaj@nvidia.com>2018-06-27 01:57:02 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-19 16:54:26 -0400
commitb1d0d8ece83ba0aa7b1e7ea9062eedc5cd9e4e33 (patch)
tree5a88d345e23e05d3a3ca9018cedcf6b12958a20b /drivers/gpu/nvgpu/gk20a/gk20a.h
parentd859c5f4a03b975dc493f72a35016e83adad279a (diff)
Revert "Revert: GV11B runlist preemption patches"
This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c. Originally change was reverted as it was making ap_compute test on embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg preempt with runlist preempt during teardown, preempt timeout set to 100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy chips) and not issuing preempt timeout recovery if preempt fails, helped resolve the issue. Bug 200426402 Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d6e0342b..17b0a60b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -685,9 +685,9 @@ struct gpu_ops {
685 struct ch_state *ch_state); 685 struct ch_state *ch_state);
686 u32 (*intr_0_error_mask)(struct gk20a *g); 686 u32 (*intr_0_error_mask)(struct gk20a *g);
687 int (*is_preempt_pending)(struct gk20a *g, u32 id, 687 int (*is_preempt_pending)(struct gk20a *g, u32 id,
688 unsigned int id_type, unsigned int timeout_rc_type); 688 unsigned int id_type);
689 int (*preempt_ch_tsg)(struct gk20a *g, u32 id, 689 int (*preempt_ch_tsg)(struct gk20a *g, u32 id,
690 unsigned int id_type, unsigned int timeout_rc_type); 690 unsigned int id_type);
691 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); 691 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
692 int (*reset_enable_hw)(struct gk20a *g); 692 int (*reset_enable_hw)(struct gk20a *g);
693 int (*setup_userd)(struct channel_gk20a *c); 693 int (*setup_userd)(struct channel_gk20a *c);
@@ -1132,7 +1132,7 @@ struct gpu_ops {
1132 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); 1132 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
1133 bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); 1133 bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
1134 bool (*is_stall_and_eng_intr_pending)(struct gk20a *g, 1134 bool (*is_stall_and_eng_intr_pending)(struct gk20a *g,
1135 u32 act_eng_id); 1135 u32 act_eng_id, u32 *eng_intr_pending);
1136 u32 (*intr_stall)(struct gk20a *g); 1136 u32 (*intr_stall)(struct gk20a *g);
1137 void (*intr_stall_pause)(struct gk20a *g); 1137 void (*intr_stall_pause)(struct gk20a *g);
1138 void (*intr_stall_resume)(struct gk20a *g); 1138 void (*intr_stall_resume)(struct gk20a *g);