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author | Vijayakumar Subbu <vsubbu@nvidia.com> | 2016-07-28 01:29:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-29 16:17:46 -0400 |
commit | b17d9708c9e9930778de43de1edf1385acb13ebd (patch) | |
tree | fc485e96cc19575d463c61c8b80a09dd89745f3f /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | 27b47b1969d7d9cdd3de9fd6f0131ad357f4b0fa (diff) |
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-45
Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1205849
(cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126)
Reviewed-on: http://git-master/r/1227256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c4744f3c..edc4a0e1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -54,6 +54,11 @@ struct acr_desc; | |||
54 | #include "debug_gk20a.h" | 54 | #include "debug_gk20a.h" |
55 | #include "sched_gk20a.h" | 55 | #include "sched_gk20a.h" |
56 | #include "gm206/bios_gm206.h" | 56 | #include "gm206/bios_gm206.h" |
57 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
58 | #include "clk/clk.h" | ||
59 | #include "perf/perf.h" | ||
60 | #endif | ||
61 | #include "gm206/bios_gm206.h" | ||
57 | 62 | ||
58 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | 63 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. |
59 | 32 ns is the resolution of ptimer. */ | 64 | 32 ns is the resolution of ptimer. */ |
@@ -607,6 +612,7 @@ struct gpu_ops { | |||
607 | } clk; | 612 | } clk; |
608 | bool privsecurity; | 613 | bool privsecurity; |
609 | bool securegpccs; | 614 | bool securegpccs; |
615 | bool pmupstate; | ||
610 | struct { | 616 | struct { |
611 | const struct regop_offset_range* ( | 617 | const struct regop_offset_range* ( |
612 | *get_global_whitelist_ranges)(void); | 618 | *get_global_whitelist_ranges)(void); |
@@ -717,6 +723,7 @@ struct nvgpu_bios { | |||
717 | 723 | ||
718 | struct bit_token *perf_token; | 724 | struct bit_token *perf_token; |
719 | struct bit_token *clock_token; | 725 | struct bit_token *clock_token; |
726 | struct bit_token *virt_token; | ||
720 | u32 expansion_rom_offset; | 727 | u32 expansion_rom_offset; |
721 | }; | 728 | }; |
722 | 729 | ||
@@ -746,6 +753,10 @@ struct gk20a { | |||
746 | struct pmu_gk20a pmu; | 753 | struct pmu_gk20a pmu; |
747 | struct acr_desc acr; | 754 | struct acr_desc acr; |
748 | struct cooling_device_gk20a gk20a_cdev; | 755 | struct cooling_device_gk20a gk20a_cdev; |
756 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
757 | struct clk_pmupstate clk_pmu; | ||
758 | struct perf_pmupstate perf_pmu; | ||
759 | #endif | ||
749 | 760 | ||
750 | #ifdef CONFIG_DEBUG_FS | 761 | #ifdef CONFIG_DEBUG_FS |
751 | struct railgate_stats pstats; | 762 | struct railgate_stats pstats; |
@@ -992,6 +1003,7 @@ enum gk20a_dbg_categories { | |||
992 | gpu_dbg_map_v = BIT(14), /* verbose mem mappings */ | 1003 | gpu_dbg_map_v = BIT(14), /* verbose mem mappings */ |
993 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ | 1004 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ |
994 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ | 1005 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ |
1006 | gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */ | ||
995 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ | 1007 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ |
996 | }; | 1008 | }; |
997 | 1009 | ||