gpu: nvgpu: Control comptagline assignment from kernel

On Maxwell comptaglines are assigned per 128k, but preferred big page
size for graphics is 64k. Bit 16 of GPU VA is used for determining
which half of comptagline is used.

This creates problems if user space wants to map a page multiple times
and to arbitrary GPU VA. In one mapping the page might be mapped to
lower half of 128k comptagline, and in another mapping the page might
be mapped to upper half.

Turn on mode where MSB of comptagline in PTE is used instead of bit 16
for determining the comptagline lower/upper half selection.

Bug 1704834

Change-Id: If87e8f6ac0fc9c5624e80fa1ba2ceeb02781355b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/924322
Reviewed-by: Alex Waterman <alexw@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d3dc03e7..6f2258e9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -197,6 +197,7 @@ struct gpu_ops {
                 void (*init_uncompressed_kind_map)(struct gk20a *g);
                 void (*init_kind_attr)(struct gk20a *g);
                 void (*set_mmu_page_size)(struct gk20a *g);
+                bool (*set_use_full_comp_tag_line)(struct gk20a *g);
                 int (*compression_page_size)(struct gk20a *g);
                 int (*compressible_page_size)(struct gk20a *g);
                 void (*dump_vpr_wpr_info)(struct gk20a *g);