gpu: nvgpu: fix zcull programming

There are eight tiles per map tile register and
depending on how many tpcs are present, there is
a chance that s/w will be accessing un-allocated
memory for reading tile values from temp buffers.

Bug 1735760

Change-Id: I5c0e09ec75099aaf6ad03dde964b9e93c2dc2408
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1221580
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a76798d1..933ab4a9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -305,6 +305,8 @@ struct gpu_ops {
                 void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc);
                 int  (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr);
                 int (*init_sw_veid_bundle)(struct gk20a *g);
+                void (*program_zcull_mapping)(struct gk20a *g,
+                                u32 zcull_alloc_num, u32 *zcull_map_tiles);
         } gr;
         const char *name;
         struct {