gpu: nvgpu: Move therm HAL to common

Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.

Bump gk20a code to gm20b.

JIRA NVGPU-955

Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 14 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 204fd371..5bb91f62 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter;
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
 #include "pmu_gk20a.h"
-#include "therm_gk20a.h"
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
@@ -161,6 +160,18 @@ struct nvgpu_gpfifo_userdata {
 #define NVGPU_FB_MMU_FAULT_BUF_DISABLED                 0U
 #define NVGPU_FB_MMU_FAULT_BUF_ENABLED                  1U
 
+/* Parameters for init_elcg_mode/init_blcg_mode */
+enum {
+        ELCG_RUN,       /* clk always run, i.e. disable elcg */
+        ELCG_STOP,      /* clk is stopped */
+        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
+};
+
+enum {
+        BLCG_RUN,       /* clk always run, i.e. disable blcg */
+        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
+};
+
 struct gpu_ops {
         struct {
                 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -425,7 +436,6 @@ struct gpu_ops {
                                         struct nvgpu_mem *mem, u64 gpu_va);
                 void (*set_preemption_buffer_va)(struct gk20a *g,
                                         struct nvgpu_mem *mem, u64 gpu_va);
-                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 void (*load_tpc_mask)(struct gk20a *g);
                 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*trigger_suspend)(struct gk20a *g);
@@ -979,6 +989,8 @@ struct gpu_ops {
         } pramin;
         struct {
                 int (*init_therm_setup_hw)(struct gk20a *g);
+                void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
+                void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine);
                 int (*elcg_init_idle_filters)(struct gk20a *g);
 #ifdef CONFIG_DEBUG_FS
                 void (*therm_debugfs_init)(struct gk20a *g);