gpu: nvgpu: Add check_priv_security fuse ops

-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
 and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
 during hal initialization

-For igpu non simulation platforms, fuses are read
 to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
  is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
  in LS mode and this needs wpr_enabled set to 1
  AND vpr_auto_fetch_disable set to 0. In this case
  gmmu tries to pull wpr and vpr settings from tegra mc

Bug 2018223

Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8d8bfbec..8d6db4c7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1024,6 +1024,10 @@ struct gpu_ops {
         struct {
                 void (*isr)(struct gk20a *g);
         } priv_ring;
+        struct {
+                int (*check_priv_security)(struct gk20a *g);
+        } fuse;
+
 };
 
 struct nvgpu_bios_ucode {