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authorRichard Zhao <rizhao@nvidia.com>2018-06-26 20:37:40 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-19 19:43:58 -0400
commit7f14aafc2c02eb0fab458324d0ba91a7fdea3086 (patch)
treecda9f48839fbde3444fde521a9b0069eb06cd81a /drivers/gpu/nvgpu/gk20a/gk20a.h
parent5ff1b3fe5a30c926e59a55ad25dd4daf430c8579 (diff)
gpu: nvgpu: rework ecc structure and sysfs
- create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7cb8462f..e69036d7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -35,7 +35,6 @@ struct gk20a_ctxsw_trace;
35struct acr_desc; 35struct acr_desc;
36struct nvgpu_mem_alloc_tracker; 36struct nvgpu_mem_alloc_tracker;
37struct dbg_profiler_object_data; 37struct dbg_profiler_object_data;
38struct ecc_gk20a;
39struct gk20a_debug_output; 38struct gk20a_debug_output;
40struct nvgpu_clk_pll_debug_data; 39struct nvgpu_clk_pll_debug_data;
41struct nvgpu_nvhost_dev; 40struct nvgpu_nvhost_dev;
@@ -64,6 +63,7 @@ struct nvgpu_ctxsw_trace_filter;
64#include <nvgpu/clk_arb.h> 63#include <nvgpu/clk_arb.h>
65#include <nvgpu/nvlink.h> 64#include <nvgpu/nvlink.h>
66#include <nvgpu/sim.h> 65#include <nvgpu/sim.h>
66#include <nvgpu/ecc.h>
67 67
68#include "clk_gk20a.h" 68#include "clk_gk20a.h"
69#include "ce2_gk20a.h" 69#include "ce2_gk20a.h"
@@ -77,7 +77,6 @@ struct nvgpu_ctxsw_trace_filter;
77#include "perf/perf.h" 77#include "perf/perf.h"
78#include "pmgr/pmgr.h" 78#include "pmgr/pmgr.h"
79#include "therm/thrm.h" 79#include "therm/thrm.h"
80#include "ecc_gk20a.h"
81 80
82/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. 81/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
83 32 ns is the resolution of ptimer. */ 82 32 ns is the resolution of ptimer. */
@@ -384,8 +383,7 @@ struct gpu_ops {
384 u32 gpc_exception); 383 u32 gpc_exception);
385 void (*enable_gpc_exceptions)(struct gk20a *g); 384 void (*enable_gpc_exceptions)(struct gk20a *g);
386 void (*enable_exceptions)(struct gk20a *g); 385 void (*enable_exceptions)(struct gk20a *g);
387 void (*create_gr_sysfs)(struct gk20a *g); 386 int (*init_ecc)(struct gk20a *g);
388 void (*remove_gr_sysfs)(struct gk20a *g);
389 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); 387 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
390 int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc, 388 int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc,
391 u32 sm, struct channel_gk20a *fault_ch); 389 u32 sm, struct channel_gk20a *fault_ch);
@@ -1385,7 +1383,7 @@ struct gk20a {
1385 struct mm_gk20a mm; 1383 struct mm_gk20a mm;
1386 struct nvgpu_pmu pmu; 1384 struct nvgpu_pmu pmu;
1387 struct acr_desc acr; 1385 struct acr_desc acr;
1388 struct ecc_gk20a ecc; 1386 struct nvgpu_ecc ecc;
1389 struct clk_pmupstate clk_pmu; 1387 struct clk_pmupstate clk_pmu;
1390 struct perf_pmupstate perf_pmu; 1388 struct perf_pmupstate perf_pmu;
1391 struct pmgr_pmupstate pmgr_pmu; 1389 struct pmgr_pmupstate pmgr_pmu;