gpu: nvgpu: correct calculation of sm_id for .record_sm_error_state

Starting with Volta, one TPC could have more than 1 SMs. So
.record_sm_error_state needs to have sm number as parameter.
Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r.

Let the function return logical sm_id. RM server will need it to nofify
client.

Jira EVLR-2643
Bug 200405202

Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a2b2e53f..49f2a34a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -368,8 +368,8 @@ struct gpu_ops {
                 void (*enable_exceptions)(struct gk20a *g);
                 void (*create_gr_sysfs)(struct gk20a *g);
                 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
-                int (*record_sm_error_state)(struct gk20a *g, u32 gpc,
-                                u32 tpc, struct channel_gk20a *fault_ch);
+                int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc,
+                                u32 sm, struct channel_gk20a *fault_ch);
                 int (*update_sm_error_state)(struct gk20a *g,
                                 struct channel_gk20a *ch, u32 sm_id,
                                 struct nvgpu_gr_sm_error_state *sm_error_state);