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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-04-06 16:10:32 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-15 11:48:20 -0400
commit6839341bf8ffafa115cfc0427bba694ee1d131f3 (patch)
tree1f9369a3bacf0f1a2cc23371f5de988efdc07c31 /drivers/gpu/nvgpu/gk20a/gk20a.h
parent61e009c0f8874898335e6c47a610233c3382be47 (diff)
gpu: nvgpu: Add litter values HAL
Move per-chip constants to be returned by a chip specific function. Implement get_litter_value() for each chip. Change-Id: I2a2730fce14010924d2507f6fa15cc2ea0795113 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1121383
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h31
1 files changed, 29 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 71271a2c..e17392d0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -72,6 +72,32 @@ enum gk20a_cbc_op {
72#define MC_INTR_UNIT_DISABLE false 72#define MC_INTR_UNIT_DISABLE false
73#define MC_INTR_UNIT_ENABLE true 73#define MC_INTR_UNIT_ENABLE true
74 74
75enum nvgpu_litter_value {
76 GPU_LIT_NUM_GPCS,
77 GPU_LIT_NUM_PES_PER_GPC,
78 GPU_LIT_NUM_ZCULL_BANKS,
79 GPU_LIT_NUM_TPC_PER_GPC,
80 GPU_LIT_NUM_FBPS,
81 GPU_LIT_GPC_BASE,
82 GPU_LIT_GPC_STRIDE,
83 GPU_LIT_GPC_SHARED_BASE,
84 GPU_LIT_TPC_IN_GPC_BASE,
85 GPU_LIT_TPC_IN_GPC_STRIDE,
86 GPU_LIT_TPC_IN_GPC_SHARED_BASE,
87 GPU_LIT_PPC_IN_GPC_BASE,
88 GPU_LIT_PPC_IN_GPC_STRIDE,
89 GPU_LIT_ROP_BASE,
90 GPU_LIT_ROP_STRIDE,
91 GPU_LIT_ROP_SHARED_BASE,
92 GPU_LIT_HOST_NUM_PBDMA,
93 GPU_LIT_LTC_STRIDE,
94 GPU_LIT_LTS_STRIDE,
95 GPU_LIT_NUM_FBPAS,
96 GPU_LIT_FBPA_STRIDE,
97};
98
99#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
100
75struct gpu_ops { 101struct gpu_ops {
76 struct { 102 struct {
77 int (*determine_L2_size_bytes)(struct gk20a *gk20a); 103 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -151,8 +177,8 @@ struct gpu_ops {
151 u32 mode); 177 u32 mode);
152 int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, 178 int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr,
153 struct gr_zcull_info *zcull_params); 179 struct gr_zcull_info *zcull_params);
154 bool (*is_tpc_addr)(u32 addr); 180 bool (*is_tpc_addr)(struct gk20a *g, u32 addr);
155 u32 (*get_tpc_num)(u32 addr); 181 u32 (*get_tpc_num)(struct gk20a *g, u32 addr);
156 void (*detect_sm_arch)(struct gk20a *g); 182 void (*detect_sm_arch)(struct gk20a *g);
157 int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr, 183 int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr,
158 struct zbc_entry *color_val, u32 index); 184 struct zbc_entry *color_val, u32 index);
@@ -526,6 +552,7 @@ struct gpu_ops {
526 size_t scatter_buffer_size); 552 size_t scatter_buffer_size);
527 } cde; 553 } cde;
528 554
555 int (*get_litter_value)(struct gk20a *g, enum nvgpu_litter_value value);
529 int (*chip_init_gpu_characteristics)(struct gk20a *g); 556 int (*chip_init_gpu_characteristics)(struct gk20a *g);
530}; 557};
531 558