diff options
author | Lakshmanan M <lm@nvidia.com> | 2016-06-02 00:04:46 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-07 15:31:34 -0400 |
commit | 6299b00beb9dabdd53c211b02658d022827b3232 (patch) | |
tree | 941d8dd8aae8f7f8c73329e182984c36a5a9bf88 /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | 3d7263d3cafdcfc57a6d6b9f829562845d116294 (diff) |
gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt handling support
for gm206 GPU family
5) Added generic mechanism to identify the
CE engine pri_base address for gm206
(CE0, CE1 and CE2)
6) Removed hard coded engine_id logic and
made generic way
7) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1155963
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3da19cc8..b7f3f6f1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -90,6 +90,7 @@ enum nvgpu_litter_value { | |||
90 | GPU_LIT_ROP_BASE, | 90 | GPU_LIT_ROP_BASE, |
91 | GPU_LIT_ROP_STRIDE, | 91 | GPU_LIT_ROP_STRIDE, |
92 | GPU_LIT_ROP_SHARED_BASE, | 92 | GPU_LIT_ROP_SHARED_BASE, |
93 | GPU_LIT_HOST_NUM_ENGINES, | ||
93 | GPU_LIT_HOST_NUM_PBDMA, | 94 | GPU_LIT_HOST_NUM_PBDMA, |
94 | GPU_LIT_LTC_STRIDE, | 95 | GPU_LIT_LTC_STRIDE, |
95 | GPU_LIT_LTS_STRIDE, | 96 | GPU_LIT_LTS_STRIDE, |
@@ -120,8 +121,8 @@ struct gpu_ops { | |||
120 | void (*flush)(struct gk20a *g); | 121 | void (*flush)(struct gk20a *g); |
121 | } ltc; | 122 | } ltc; |
122 | struct { | 123 | struct { |
123 | void (*isr_stall)(struct gk20a *g); | 124 | void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
124 | void (*isr_nonstall)(struct gk20a *g); | 125 | void (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
125 | } ce2; | 126 | } ce2; |
126 | struct { | 127 | struct { |
127 | int (*init_fs_state)(struct gk20a *g); | 128 | int (*init_fs_state)(struct gk20a *g); |
@@ -350,6 +351,7 @@ struct gpu_ops { | |||
350 | int (*tsg_bind_channel)(struct tsg_gk20a *tsg, | 351 | int (*tsg_bind_channel)(struct tsg_gk20a *tsg, |
351 | struct channel_gk20a *ch); | 352 | struct channel_gk20a *ch); |
352 | int (*tsg_unbind_channel)(struct channel_gk20a *ch); | 353 | int (*tsg_unbind_channel)(struct channel_gk20a *ch); |
354 | u32 (*eng_runlist_base_size)(void); | ||
353 | } fifo; | 355 | } fifo; |
354 | struct pmu_v { | 356 | struct pmu_v { |
355 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 357 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |