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authorKonsta Holtta <kholtta@nvidia.com>2015-03-06 09:33:43 -0500
committerTerje Bergstrom <tbergstrom@nvidia.com>2015-06-09 14:13:43 -0400
commit6085c90f499c642bc41a646b0efbdfe60e096c74 (patch)
tree0eaab99b228ce162ec3a44d0f8138b441f5a64f4 /drivers/gpu/nvgpu/gk20a/gk20a.h
parenta41e5c41cadaa3d030a1f75b09328b8b1a440b69 (diff)
gpu: nvgpu: add per-channel refcounting
Add reference counting for channels, and wait for reference count to get to 0 in gk20a_channel_free() before actually freeing the channel. Also, change free channel tracking a bit by employing a list of free channels, which simplifies the procedure of finding available channels with reference counting. Each use of a channel must have a reference taken before use or held by the caller. Taking a reference of a wild channel pointer may fail, if the channel is either not opened or in a process of being closed. Also, add safeguards for protecting accidental use of closed channels, specifically, by setting ch->g = NULL in channel free. This will make it obvious if freed channel is attempted to be used. The last user of a channel might be the deferred interrupt handler, so wait for deferred interrupts to be processed twice in the channel free procedure: once for providing last notifications to the channel and once to make sure there are no stale pointers left after referencing to the channel has been denied. Finally, fix some races in channel and TSG force reset IOCTL path, by pausing the channel scheduler in gk20a_fifo_recover_ch() and gk20a_fifo_recover_tsg(), while the affected engines have been identified, the appropriate MMU faults triggered, and the MMU faults handled. In this case, make sure that the MMU fault does not attempt to query the hardware about the failing channel or TSG ids. This should make channel recovery more safe also in the regular (i.e., not in the interrupt handler) context. Bug 1530226 Bug 1597493 Bug 1625901 Bug 200076344 Bug 200071810 Change-Id: Ib274876908e18219c64ea41e50ca443df81d957b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/448463 (cherry picked from commit 3f03aeae64ef2af4829e06f5f63062e8ebd21353) Reviewed-on: http://git-master/r/755147 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a52d97f3..d8e3586f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -538,6 +538,15 @@ struct gk20a {
538 u32 max_ltc_count; 538 u32 max_ltc_count;
539 u32 ltc_count; 539 u32 ltc_count;
540 540
541 atomic_t hw_irq_stall_count;
542 atomic_t hw_irq_nonstall_count;
543
544 atomic_t sw_irq_stall_last_handled;
545 wait_queue_head_t sw_irq_stall_last_handled_wq;
546
547 atomic_t sw_irq_nonstall_last_handled;
548 wait_queue_head_t sw_irq_nonstall_last_handled_wq;
549
541 struct devfreq *devfreq; 550 struct devfreq *devfreq;
542 551
543 struct gk20a_scale_profile *scale_profile; 552 struct gk20a_scale_profile *scale_profile;