gpu: nvgpu: Use PMU ver to check ZBC support.

From Volta onwards, new DSS ZBC registers are
added for ZBC feature and save/restore of new
ZBC reglist is taken care by ctxsw firmware.
Therefore, PMU should save ZBC reglist only
for PRE-volta chips.

JIRA GPUT19X-20

Change-Id: I7d92274208ca42cc77bf57ea3cc416b5ecf32842
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1460244
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 9760ba35..85878423 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -481,6 +481,7 @@ struct gpu_ops {
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
                 u32 cmd_id_zbc_table_update;
+                bool is_pmu_zbc_save_supported;
                 u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu);
                 void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu,
                         u32 freq);