gpu: nvgpu: reorganize PMU IPC

- Moved PMU IPC related code to
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file,
-Below is the list which are moved
  seq
  mutex
  queue
  cmd/msg post & process
  event handling

NVGPU-56

Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1478167
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index b4884af1..269f0d68 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -737,6 +737,14 @@ struct gpu_ops {
                 u32 (*pmu_get_queue_head_size)(void);
                 u32 (*pmu_get_queue_tail_size)(void);
                 u32 (*pmu_get_queue_tail)(u32 i);
+                int (*pmu_queue_head)(struct nvgpu_pmu *pmu,
+                        struct pmu_queue *queue, u32 *head, bool set);
+                int (*pmu_queue_tail)(struct nvgpu_pmu *pmu,
+                        struct pmu_queue *queue, u32 *tail, bool set);
+                int (*pmu_mutex_acquire)(struct nvgpu_pmu *pmu,
+                        u32 id, u32 *token);
+                int (*pmu_mutex_release)(struct nvgpu_pmu *pmu,
+                        u32 id, u32 *token);
                 int (*init_wpr_region)(struct gk20a *g);
                 int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
                 void (*write_dmatrfbase)(struct gk20a *g, u32 addr);