gpu: nvgpu: initialze bundle64 state

We receive bundle with address and 64 bit values from ucode on some platforms
This patch adds the support to handle 64 bit values

Add struct av64_gk20a to store an address and corresponding 64 bit value
Add struct av64_list_gk20a to store count and list of av64_gk20a

Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit
values

In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT,
load the bundle64 state into above local structures

Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle()
if defined

Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim()

Jira NVGPUT-96

Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1736450
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f7bec806..48f0008a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -475,6 +475,7 @@ struct gpu_ops {
                                         u32 *priv_addr_table,
                                         u32 *priv_addr_table_index);
                 u32 (*fecs_ctxsw_mailbox_size)(void);
+                int (*init_sw_bundle64)(struct gk20a *g);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);