diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-15 12:04:15 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-17 15:29:09 -0500 |
commit | 2f6698b863c9cc1db6455637b7c72e812b470b93 (patch) | |
tree | d0c8abf32d6994b9f54bf5eddafd8316e038c829 /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | 6a73114788ffafe4c53771c707ecbd9c9ea0a117 (diff) |
gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 070b26b6..685976b1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -187,16 +187,16 @@ struct gpu_ops { | |||
187 | void (*cb_size_default)(struct gk20a *g); | 187 | void (*cb_size_default)(struct gk20a *g); |
188 | int (*calc_global_ctx_buffer_size)(struct gk20a *g); | 188 | int (*calc_global_ctx_buffer_size)(struct gk20a *g); |
189 | void (*commit_global_attrib_cb)(struct gk20a *g, | 189 | void (*commit_global_attrib_cb)(struct gk20a *g, |
190 | struct channel_ctx_gk20a *ch_ctx, | 190 | struct nvgpu_gr_ctx *ch_ctx, |
191 | u64 addr, bool patch); | 191 | u64 addr, bool patch); |
192 | void (*commit_global_bundle_cb)(struct gk20a *g, | 192 | void (*commit_global_bundle_cb)(struct gk20a *g, |
193 | struct channel_ctx_gk20a *ch_ctx, | 193 | struct nvgpu_gr_ctx *ch_ctx, |
194 | u64 addr, u64 size, bool patch); | 194 | u64 addr, u64 size, bool patch); |
195 | int (*commit_global_cb_manager)(struct gk20a *g, | 195 | int (*commit_global_cb_manager)(struct gk20a *g, |
196 | struct channel_gk20a *ch, | 196 | struct channel_gk20a *ch, |
197 | bool patch); | 197 | bool patch); |
198 | void (*commit_global_pagepool)(struct gk20a *g, | 198 | void (*commit_global_pagepool)(struct gk20a *g, |
199 | struct channel_ctx_gk20a *ch_ctx, | 199 | struct nvgpu_gr_ctx *ch_ctx, |
200 | u64 addr, u32 size, bool patch); | 200 | u64 addr, u32 size, bool patch); |
201 | void (*init_gpc_mmu)(struct gk20a *g); | 201 | void (*init_gpc_mmu)(struct gk20a *g); |
202 | int (*handle_sw_method)(struct gk20a *g, u32 addr, | 202 | int (*handle_sw_method)(struct gk20a *g, u32 addr, |
@@ -230,7 +230,6 @@ struct gpu_ops { | |||
230 | int (*load_ctxsw_ucode)(struct gk20a *g); | 230 | int (*load_ctxsw_ucode)(struct gk20a *g); |
231 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 231 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
232 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 232 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
233 | void (*free_channel_ctx)(struct channel_gk20a *c, bool is_tsg); | ||
234 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 233 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
235 | u32 class_num, u32 flags); | 234 | u32 class_num, u32 flags); |
236 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, | 235 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, |
@@ -285,13 +284,12 @@ struct gpu_ops { | |||
285 | u32 (*pagepool_default_size)(struct gk20a *g); | 284 | u32 (*pagepool_default_size)(struct gk20a *g); |
286 | int (*init_ctx_state)(struct gk20a *g); | 285 | int (*init_ctx_state)(struct gk20a *g); |
287 | int (*alloc_gr_ctx)(struct gk20a *g, | 286 | int (*alloc_gr_ctx)(struct gk20a *g, |
288 | struct gr_ctx_desc **__gr_ctx, struct vm_gk20a *vm, | 287 | struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm, |
289 | u32 class, u32 padding); | 288 | u32 class, u32 padding); |
290 | void (*free_gr_ctx)(struct gk20a *g, | 289 | void (*free_gr_ctx)(struct gk20a *g, |
291 | struct vm_gk20a *vm, | 290 | struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); |
292 | struct gr_ctx_desc *gr_ctx); | ||
293 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, | 291 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, |
294 | struct channel_ctx_gk20a *ch_ctx, | 292 | struct channel_gk20a *c, |
295 | struct nvgpu_mem *mem); | 293 | struct nvgpu_mem *mem); |
296 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, | 294 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, |
297 | struct channel_gk20a *c, | 295 | struct channel_gk20a *c, |
@@ -384,14 +382,14 @@ struct gpu_ops { | |||
384 | int (*get_preemption_mode_flags)(struct gk20a *g, | 382 | int (*get_preemption_mode_flags)(struct gk20a *g, |
385 | struct nvgpu_preemption_modes_rec *preemption_modes_rec); | 383 | struct nvgpu_preemption_modes_rec *preemption_modes_rec); |
386 | int (*set_ctxsw_preemption_mode)(struct gk20a *g, | 384 | int (*set_ctxsw_preemption_mode)(struct gk20a *g, |
387 | struct gr_ctx_desc *gr_ctx, | 385 | struct nvgpu_gr_ctx *gr_ctx, |
388 | struct vm_gk20a *vm, u32 class, | 386 | struct vm_gk20a *vm, u32 class, |
389 | u32 graphics_preempt_mode, | 387 | u32 graphics_preempt_mode, |
390 | u32 compute_preempt_mode); | 388 | u32 compute_preempt_mode); |
391 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); | 389 | int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost); |
392 | void (*update_boosted_ctx)(struct gk20a *g, | 390 | void (*update_boosted_ctx)(struct gk20a *g, |
393 | struct nvgpu_mem *mem, | 391 | struct nvgpu_mem *mem, |
394 | struct gr_ctx_desc *gr_ctx); | 392 | struct nvgpu_gr_ctx *gr_ctx); |
395 | int (*init_sm_id_table)(struct gk20a *g); | 393 | int (*init_sm_id_table)(struct gk20a *g); |
396 | int (*load_smid_config)(struct gk20a *g); | 394 | int (*load_smid_config)(struct gk20a *g); |
397 | void (*program_sm_id_numbering)(struct gk20a *g, | 395 | void (*program_sm_id_numbering)(struct gk20a *g, |
@@ -440,7 +438,7 @@ struct gpu_ops { | |||
440 | u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); | 438 | u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); |
441 | u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); | 439 | u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); |
442 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, | 440 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, |
443 | struct gr_ctx_desc *gr_ctx); | 441 | struct nvgpu_gr_ctx *gr_ctx); |
444 | } gr; | 442 | } gr; |
445 | struct { | 443 | struct { |
446 | void (*init_hw)(struct gk20a *g); | 444 | void (*init_hw)(struct gk20a *g); |