gpu: nvgpu: Support multiple SM for t19x

-Add sm input param for handle_sm_exception and
pre_process_sm_exception for gr ops/functions.
-Add functions to calculate gpc and tpc reg offsets.
-Add function to find SMs which raised SM exception.

JIRA GPUT19X-75

Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1476108
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>

1 files changed, 8 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8f291f92..e0434360 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -285,12 +285,15 @@ struct gpu_ops {
                                 struct channel_gk20a *ch,
                                 struct gr_gk20a_isr_data *isr_data);
                 int (*pre_process_sm_exception)(struct gk20a *g,
-                                u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr,
-                                bool sm_debugger_attached,
-                                struct channel_gk20a *fault_ch,
-                                bool *early_exit, bool *ignore_debugger);
+                        u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
+                        bool sm_debugger_attached,
+                        struct channel_gk20a *fault_ch,
+                        bool *early_exit, bool *ignore_debugger);
                 u32 (*mask_hww_warp_esr)(u32 hww_warp_esr);
-                int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc,
+                void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
+                                         u32 *esr_sm_sel);
+                int (*handle_sm_exception)(struct gk20a *g,
+                        u32 gpc, u32 tpc, u32 sm,
                         bool *post_event, struct channel_gk20a *fault_ch,
                         u32 *hww_global_esr);
                 int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc,